cn8236 Mindspeed Technologies, cn8236 Datasheet - Page 325

• Manufacturer Part Number: cn8236
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

CN8236
ATM ServiceSAR Plus with xBR Traffic Management
14.3 Segmentation Registers
0x80
This register contains general control bits for the segmentation coprocessor. The assertion of the HRST* system
reset pin or GLOBAL_RESET bit in the CONFIG0 register causes the clearing of the SEG_ENABLE control bit.
28236-DSH-001-B
29–27
21–16
15–12
10–6
Bit
31
30
26
25
24
23
22
11
5
4
—
Segmentation Control Register (SEG_CTRL)
Field
Size
1
1
3
1
1
1
1
1
6
4
1
5
1
1
SEG_ENABLE
SEG_RESET
VBR_OFFSET
SEG_GFC
DBL_SLOT
CBR_TUN
ADV_ABR_TMPLT
USE_SCH_CTRL
Reserved
TX_FIFO_LEN
CLP0_EOM
OAM_STAT_ID
SEG_ST_HALT
SEG_LS_DIS
Name
Mindspeed Technologies
Segmentation Enable—enables segmentation coprocessor. If disabled, the
segmentation coprocessor halts on a cell boundary.
Segmentation Reset—resets segmentation coprocessor and pointers.
Offset from schedule slot priority to general priority.
(VBR_OFFSET + (# VBR / ABR priorities) 7.) Not active if
USE_SCH_CTRL is asserted.
Enable segmentation GFC processing. The segmentation machine is
disabled when the SAR receives cells with GFC halt set. GFC priority
queues (set in the SCH_PRI register) are active for one cell for each
received cell with GFC SET_A bit = 1.
Each schedule slot occupies two words. Not active if USE_SCH_CTRL is
asserted.
Use first entry in each schedule slot for CBR/tunnel traffic.
Advanced ABR template mode. When logic high, per-connection MCR and
ICR enabled. When logic low, per-template MCR and ICR enabled.
Activate the use of SLOT_DEPTH, the 4-bit VBR_OFFSET field, and
TUN_PRI0_OFFSET from the SCH_CTRL register. Deactivate the use of
DBL_SLOT and the 3-bit VBR_OFFSET field from the SEG_CTRL register.
This bit cannot be set to a logic high in 8235 mode.
Program and read as 0.
Depth of transmit FIFO buffer in cells. Valid range is 3–9. To ensure
optimum performance, the depth of the FIFO buffer should be at least
three.
Set CLP in ATM header to 0 on last cell of CPCS-PDU.
Status queue ID for buffer descriptors with OAM_STAT set.
Enables a status queue entry for a VCC halted with a partially segmented
packet.
Segmentation Local Status Disable—Disable segmentation check for
SAR-shared memory status queue full condition. If this bit is not set, the
segmentation coprocessor does not segment any cells for a VCC assigned
to a full SAR-shared memory status queue. This bit can be used to disable
overflow checking when the queues are sized large enough to prevent
overflow.
™
Description
14.3 Segmentation Registers
14.0 CN8236 Registers
14-9