cn8236 Mindspeed Technologies, cn8236 Datasheet - Page 144

• Manufacturer Part Number: cn8236
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

5.0 Reassembly Coprocessor
5.6 Status Queue Operation
5-34
5.6.1.2 Operation
5.6.1.3 Errors
The reassembly coprocessor normally writes a status queue entry when a
complete CPCS-PDU has been reassembled. It also writes a status queue entry for
each received OAM cell.
bit in the entry to a logic high and increments the WRITE pointer in the status
queue base table entry for that status queue.
READ pointer for that status queue. It reads only the VLD bit at first before
reading any other word to maintain data coherency.
queue entry, increments the host READ counter, and resets the VLD bit to a logic
low. The host also periodically writes the READ counter value to the READ_UD
field in the status queue base table entry for that queue.
completion of a CPCS-PDU. Optionally, a status entry can be written at both the
beginning and end of a message to allow the host to initiate protocol header
processing in advance of receiving the complete message. The host can then
traverse the linked cell buffers to collect the complete CPCS-PDU.
coprocessor writes an additional status queue entry at the completion of the first
buffer of a CPCS-PDU. This status queue entry is delineated by the BOM bit set
and the EOM bit cleared. This allows the host to begin packet processing before
reception of the complete CPCS-PDU. In this case only the BD_PNTR and
VCC_INDEX fields are valid in that status queue entry.
activates Streaming Mode for that channel. In this mode, the RSM coprocessor
writes a status entry for each completed buffer. The BD_PNTR field in the status
entry points to the corresponding buffer descriptor for that single buffer. Only the
last status entry for that CPCS-PDU, with EOM bit a logic high, contains valid
status data for that PDU.
queues.
The RSM coprocessor also writes a status entry for several error conditions:
reassembled on channels having free buffer queues in the empty state, a BOM cell
causes a status queue entry to be written. If a BOM cell is received and no early
packet discards have occurred on channels mapped to the empty free buffer
queue, status queue entry is written with the BOM and UNDF bits set to a logic
high. In addition, either the RSM_HF_EMPT bit in the HOST_ISTAT1 register or
the RSM_LF_EMPT bit in the LP_ISTAT1 register is set to a logic high. This
status does not point to a linked list of buffer descriptors. It is written a maximum
of once per free buffer queue empty condition.
Each time the RSM coprocessor writes a status queue entry, it sets the VLD
When the host processes the status queue, it reads entries based on the host
When the host finds the VLD bit set to a logic high, it processes the status
When in Message Mode, the RSM coprocessor writes a status entry at the
If the BINTR bit in the RSM VCC table entry is a logic high, the RSM
The STM_MODE bit in the RSM VCC table, being set to a logic high,
Refer to
• Reassembly time-out
• Early packet discard
• Per-channel firewall
• CPCS abort
To ensure that an error indication occurs even if no CPCS-PDUs are being
Mindspeed Technologies
Chapter
2.0, for detailed information on the operation of status
ATM ServiceSAR Plus with xBR Traffic Management
™
28236-DSH-001-B
CN8236