89ttm552 Integrated Device Technology, 89ttm552 Datasheet - Page 10

• Manufacturer Part Number: 89ttm552
• Description: Standalone 10g Simplex Traffic Manager
• Manufacturer: Integrated Device Technology

IDT 89TTM552
PLL_RST
PLL_DIV_RST
PLL_CFG_OVR
PLL_SYS_REFCLK
PLL_DDR_BYPCLK
PLL_SYS_LCK
PLL_SYS_MON
PLL_RX_REFCLK
ZBUS_CLK
ZBUS_GNT_N
ZBUS_DEVID[4:0]
ZBUS_INT_N[2:0]
ZBUS_DIR
ZBUS_REQ_N
ZBUS_AD[31:0]
ZBUS_PRTY[1:0]
ZBUS_AVALID_N
ZBUS_DVALID_N
Signal Name
Signal Name
100K internal pulldown
100K internal pulldown
100K internal pulldown
100K internal pullup
100K internal pullup
100K internal pullup
100K internal pullup
100K internal pullup
100K internal pullup
100K internal pullup
3.3V, 16 mA drive
3.3V, 16 mA drive
3.3V, 16 mA drive
3.3V, 16mA drive
no internal pullup
3.3V, 16mA drive
3.3V LVTTL,
3.3V LVTTL,
3.3V LVTTL,
3.3V LVTTL,
I/O Type
16mA drive,
16mA drive,
16mA drive,
16mA drive,
I/O Type
3.3V,
3.3V,
3.3V,
3.3V,
3.3V,
3.3V,
3.3V,
3.3V
Table 9 Processor Interface (ZBus)
Dir.
Table 10 PLL (Part 1 of 2)
B
O
O
O
B
B
B
B
I
I
Dir.
O
O
I
I
I
I
I
I
10 of 37
Freq.
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
33 or
33 or
33 or
33 or
33 or
33 or
33 or
33 or
33 or
33 or
100 MHz
100 MHz
Freq.
—
—
—
—
—
—
ZBus clock input (up to 66 MHz)
ZBus grant (active low)
Used for ZBus device identification
ZBus device interrupt (active low)
ZBus write/read flag
ZBus master cycle request (active low)
ZBus 32-bit multiplexed address/data bus
ZBus parity over address/data; one parity bit for 16 bits
ZBus address valid flag (active low)
ZBus data valid flag (active low)
PLL reset. A special initialization sequence is required.
PLL post-divider reset. A special initialization sequence is
required.
PLL latch-on-reset override input. When high, the PLLs’ con-
figurations can be latched through ZBUS_AD when RESET_N
deactivates. A special initialization sequence is required.
Chip core PLL reference clock.
Core DDR bypass clock source.
For IDT use only. Do not connect.
Core PLL VCO lock indicator.
For IDT use only. Do not connect.
Core PLL clock monitor output.
For IDT use only. Do not connect.
SPI4 Rx PLL reference clock
Remarks
Remarks
April 7, 2005