89ttm552 Integrated Device Technology, 89ttm552 Datasheet - Page 16

• Manufacturer Part Number: 89ttm552
• Description: Standalone 10g Simplex Traffic Manager
• Manufacturer: Integrated Device Technology

IDT 89TTM552
1.
1.
1.
The parameter is specified at 89TTM55x core clock frequency of 175 MHz.
The parameter is specified at 89TTM55x core clock frequency of 175 MHz.
Jitter is measured peak-to-peak from fclock/1000 to fclock. Low frequency jitter is determined by the jitter of the clock reference.
Symbol
Symbol
Symbol
T
T
T
T
T
T
T
T
T
t
t
T
T
T
T
DCQSHZ
DCQSLZ
D
SKEW1
SKEW2
DCQST
DCQHZ
QSCQV
QSCQX
DCQLZ
J
QSCIS
QSCIH
SCQV
SCQX
DCAV
DCAX
COC
CLK
f
t
t
D
R
F
Statistics clock to output valid
Statistics clock to output invalid
DDR clock to address/control valid
DDR clock to address/control invalid
DDR clock to DQS transition
DDR clock to DQS Low-Z
DDR clock to DQS High-Z
DDR clock to DQ Low-Z
DDR clock to DQ High-Z
DQS clock to DQ output valid
DQS clock to DQ output invalid
DQS clock to DQ input setup
DQS clock to DQ input hold
Output clock signal frequency
Output clock signal duty percentage
Output clock signal jitter
V
V
| t
Differential skew
| t
Channel-to-channel skew
OD
OD
pHLA
pdiff [m]
fall time, 80% to 20%
rise time, 20% to 80%
– t
– t
pLHB
pdiff [n]
Parameter
| or | t
|
pHLB
– t
pLHA
Parameter
Parameter
Table 19 Statistics Interface Timing
|,
Table 20 DDR Interface Timing
Table 21 LVDS AC Parameters
16 of 37
Min
311
45
—
—
—
—
—
Typical
—
—
—
—
—
—
—
Max
0.10
0.30
0.30
500
200
55
50
Min
Min
2.3
1.1
–0.3
1.2
-0.6
—
—
—
—
0
0
0
0
1
1
1
Units
MHz
UI
UI
UI
ps
ps
%
Typical
Typical
—
—
—
—
—
—
—
—
—
—
—
—
—
Any differential pair on pack-
Any 2 signals on package
R
R
LOAD
LOAD
Conditions
Max
Max
4.5
3.3
2.4
0.6
1.8
1.8
1.8
1.8
1.6
500 MHz
—
—
—
—
500 MHz
T = 1ns
T = 1ns
= 100
= 100
1
1
1
age
1
Units
Units
± 1%
± 1%
April 7, 2005
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns