89ttm552 Integrated Device Technology, 89ttm552 Datasheet - Page 11

• Manufacturer Part Number: 89ttm552
• Description: Standalone 10g Simplex Traffic Manager
• Manufacturer: Integrated Device Technology

IDT 89TTM552
PLL_RX_LCK
PLL_RX_RST
PLL_TX_REFCLK
PLL_TX_LCK
PLL_TX_RST
SCAN_MODE_N
SCAN_SHIFT_N
TCK
TDI
TDO
TMS
TRST_N
RESET_N
IDDQ_N
TURBO_DATA[3:0]
TURBO_CLK
VDD15
Signal Name
Signal Name
Signal Name
100K internal pulldown
100K internal pulldown
100K internal pullup
100K internal pullup
100K internal pullup
100K internal pullup
100K internal pullup
100K internal pullup
100K internal pullup
3.3V, 100K internal
3.3V, 16mA drive
3.3V, 16mA drive
no internal pullup
3.3V, 16mA drive
3.3V, 16mA drive
I/O Type
I/O Type
I/O Type
pullup
3.3V,
3.3V,
3.3V,
3.3V,
3.3V,
3.3V,
3.3V,
3.3V,
3.3V
3.3V
—
Table 12 Miscellaneous Signals (Part 1 of 2)
Dir.
Dir.
Table 10 PLL (Part 2 of 2)
Table 11 Test and Debug
O
O
O
P
I
I
I
I
I
I
I
I
Dir.
O
O
I
I
I
11 of 37
175/2 MHz
175/2 MHz
Freq.
Freq.
Async
N/A
100 MHz
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—
—
—
—
—
—
—
Freq.
—
—
—
—
Scan mode input (active low).
For IDT use only. Do not connect.
Scan shift input (active low).
For IDT use only. Do not connect.
JTAG (IEEE 1149.1) clock input.
JTAG (IEEE 1149.1) test data input.
JTAG (IEEE 1149.1) test data output.
JTAG (IEEE 1149.1) test mode select
JTAG (IEEE 1149.1) test reset input.
(If JTAG is used, and JTAG pins are being driven by some
logic, we recommend driving trstn_i low whenever JTAG is not
in operation. If JTAG is not used, trstn_i can be permanently
tied low.
Chip reset input (active low)
IDDQ input (active low).
Attach to a 4.7K resistor to 3.3V.
89TTM552 to 89TSF502 “turbo mode” interface
Source-synchronous turbo mode clock to the 89TSF502
1.5V I/O power for HSTL-2 I/Os: Isolated output buffer supply
set nominally to 1.5V
SPI4 Rx PLL VCO lock indicator.
For IDT use only. Do not connect.
SPI4 Rx PLL reset/powerdown.
Tie inactive when using register-based (i.e., non-LOR) DSX
PLL configuration.
SPI4 Tx PLL reference clock.
SPI4 Tx PLL VCO lock indicator.
For IDT use only. Do not connect.
SPI4 Tx PLL reset/powerdown.
Tie inactive when using register-based (i.e., non-LOR) DSX
PLL configuration.
Remarks
Remarks
Remarks
April 7, 2005