89ttm552 Integrated Device Technology, 89ttm552 Datasheet - Page 5

• Manufacturer Part Number: 89ttm552
• Description: Standalone 10g Simplex Traffic Manager
• Manufacturer: Integrated Device Technology

89TTM552 Pin Description
89TTM552 Pin Description
89TTM552 Pin Description
89TTM552 Pin Description
modes. The NPU/system receive interface has 16-bit data, 4-bit status for LVDS and 2-bit status for LVTTL.
IDT 89TTM552
In this data sheet, direction is indicated as follows: I for In, O for Out, B for Bidirectional, and P for power.
The 89TTM552 operates the BRx and BTX interfaces with LVDS. The flexible interface can operates in either SPI-4.2, CSIX-over-LVDS, or NPF SI
Note: Information in this section is subject to change. Contact your IDT FAE before making design decisions.
FLQS_DIN[21:0],
FLQS_DIN_PRTY
FLQS_CLKIN
FLQS_TIC_IN
FLQS_DOUT[17:0],
FLQS_DOUT_PRTY
FLQS_CLKOUT
FLQS_TIC_OUT
FLQS_VREF[1:0]
PP_D, PP_PRTY
PP_CLK
PP_TIC
PP_VREF
RX_CLKP, RX_CLKN
RX_SOFP, RX_SOFN
RX_DP[15:0], RX_DN[15:0]
RX_PRTYP, RX_PRTYN
RX_STAT_CLKP,
RX_STAT_CLKN
1.
2.
The 89TTM553 shares these lines, and the I/O direction is, of course, the opposite of these.
These lines multiplex many logical signals over 5 clocks.
Signal Name
Signal Name
Signal Name
Table 1 89TTM552 / 89TTM553 “External Flow Scheduler” Control Interface
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
I/O Type
I/O Type
I/O Type
0.75V
0.75V
LVDS
LVDS
LVDS
LVDS
LVDS
Table 2 Receive Traffic Interface (BRx) (Part 1 of 2)
Table 1 External Protocol Processor Port Interface
1
Dir.
Dir.
—
—
O
O
O
Dir.
I
I
I
I
I
I
O
I
I
I
I
1
33.33 MHz
33.33 MHz
33.33 MHz
5 of 37
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
Freq.
Freq.
500 MHz
500 MHz
500 MHz
500 MHz
500 MHz
Freq.
—
—
‘External scheduler control in’ serial interface
(22 signal lines + 1 parity line)
External scheduler clock in
External scheduler cell time tick in
‘External scheduler control out’ serial interface
(18 signal lines + 1 parity line)
External scheduler clock out
External scheduler cell time tick out
HSTL reference. Nominally V
Protocol processor data and parity from external protocol pro-
cessor device
Source-synchronous protocol processor port clock from exter-
nal protocol processor device
Protocol processor port cell time tick from external protocol
processor device
HSTL reference. Nominally V
Rx data clock
Rx control input
Rx data bus input (16-bit)
Rx parity over Rx data bus
Rx status clock output
Remarks
Remarks
Remarks
DDQ
DDQ
2
/ 2, so connect to 0.75 V
/ 2, so connect to 0.75 V
April 7, 2005