ST16C654CJ68 EXAR [Exar Corporation], ST16C654CJ68 Datasheet
ST16C654CJ68
Available stocks
Related parts for ST16C654CJ68
ST16C654CJ68 Summary of contents
Page 1
... ST16C654IQ64 0° 70° C ST16C654DIQ64 0° 70° C ST16C654IQ100 Note *1: Patent Pending 5-65 PLCC Package 60 -DSRD 59 -CTSD 58 -DTRD 57 GND 56 -RTSD 55 INTD 54 -CSD 53 TXD ST16C654CJ68 52 -IOR 16 MODE 51 TXC 50 -CSC 49 INTC 48 -RTSC 47 VCC 46 -DTRC 45 -CTSC 44 -DSRC Pins Package Operating temperature 68 PLCC -40° 85° C ...
Page 2
... GND 23 35 VCC -DTRB 24 34 -DTRC -CTSB 25 33 -CTSC -DSRB 26 100 Pin QFP Package ST16C654CQ100 5-66 60 -DSRD 59 -CTSD 58 -DTRD 57 GND 56 -RTSD 55 N.C. 54 N.C. 53 TXD ST16C654CJ68 52 N.C. 68 MODE 51 TXC N.C. 48 -RTSC 47 VCC 46 -DTRC 45 -CTSC 44 -DSRC 100 -RXRDYA 99 -CDA 98 -RIA 97 RXA 96 GND ...
Page 3
Figure 2, Block Diagram 16 Mode D0-D7 -IOR -IOW RESET A0-A2 -CS A-D INT A-D -RXRDY -TXRDY -RXRDY A-D -TXRDY A-D INTSEL XTAL1 MIDI XTAL2 Rev. 4.10 ST16C654/654D Transmit Transmit FIFO Shift Registers Register Flow Control Encoder Logic Receive Receive ...
Page 4
ST16C654/654D Figure 3, Block Diagram 68 Mode D0-D7 R/-W -RESET A0-A4 -CS IRQ -RXRDY -TXRDY -RXRDY A-D -TXRDY A-D XTAL1 MIDI XTAL2 Rev. 4.10 Transmit Transmit FIFO Shift Registers Register Flow Ir Control Encoder Logic Receive Receive FIFO Shift Registers ...
Page 5
SYMBOL DESCRIPTION Symbol Pin 68 100 16/- A3-A4 20,50 17,64 CLKSEL Rev. 4.10 ST16C654/654D Signal Pin Description 64 type - I 16/68 Interface Type ...
Page 6
ST16C654/654D SYMBOL DESCRIPTION Symbol Pin 68 100 -CS A-B 16,20 13,17 -CS C-D 50,54 64,68 38,42 -CSRDY - 76 D0-D2 66-68 88-90 53-55 D3-D7 1-5 91-95 56-60 GND 6,23 96,20 14,28 GND 40,57 46,71 45,61 INT A-B 15,21 12,18 INT ...
Page 7
SYMBOL DESCRIPTION Symbol Pin 68 100 INTSEL 65 87 -IOR 52 66 -IOW 18 15 -IRQ 15 12 Rev. 4.10 ST16C654/654D Signal Pin Description 64 type dition exists. Interrupt conditions include: receiver errors, available receiver buffer data, transmit buffer empty, ...
Page 8
ST16C654/654D SYMBOL DESCRIPTION Symbol Pin 68 100 IRTX A-B - 6,24 IRTX C-D - 57,75 MIDICLK - 42 -RESET RESET 37 43 R/- Rev. 4.10 Signal Pin Description 64 type ated with the 68 mode only. In the ...
Page 9
SYMBOL DESCRIPTION Symbol Pin 68 100 -RXRDY 38 44 -RXRDY A-B - 100,31 -RXRDY C-D - 50,82 -TXRDY 39 45 Rev. 4.10 ST16C654/654D Signal Pin Description 64 type functions for Read or Write strobes. A logic transition ...
Page 10
ST16C654/654D SYMBOL DESCRIPTION Symbol Pin 68 100 -TXRDY A-B - 5,25 -TXRDY C-D - 56,81 VCC 13 10 VCC 47,64 61,86 35,52 XTAL1 35 40 XTAL2 36 41 -CD A-B 9,27 99,32 64,18 -CD C-D 43,61 49,83 31,49 -CTS A-B ...
Page 11
SYMBOL DESCRIPTION Symbol Pin 68 100 -DSR A-B 10,26 7,23 -DSR C-D 44,60 58,74 32,48 -DTR A-B 12,24 9,21 -DTR C-D 46,58 60,72 34,46 -RI A-B 8,28 98,33 63,19 -RI C-D 42,62 48,84 30,50 -RTS A-B 14,22 11,19 -RTS C-D ...
Page 12
ST16C654/654D SYMBOL DESCRIPTION Symbol Pin 68 100 RX/IRRX A-B 7,29 97,34 62,20 RX/IRRX C-D 41,63 47,85 29,51 TX/IRTX A-B 17,19 14,16 TX/IRTX C-D 51,53 65,67 39,41 Rev. 4.10 Signal 64 type I Receive Data Input RX/IRRX A-D. - These inputs ...
Page 13
GENERAL DESCRIPTION The 654 provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-paral- lel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with ...
Page 14
ST16C654/654D operation or to external MIDI oscillator for MIDI appli- cations. A separate register is provided for monitoring the realtime status of the FIFO signals -TXRDY and - RXRDY for each of the four UART channels (A-D). This reduces polling ...
Page 15
Table 4, INTERNAL REGISTER DECODE READ MODE General Register Set (THR/RHR, IER/ISR, MCR/MSR, LCR/LSR, SPR Receive Holding Register Interrupt Status Register ...
Page 16
ST16C654/654D FIFO Operation The 64 byte transmit and receive data FIFO’s are enabled by the FIFO Control Register (FCR) bit-0. With 16C554 devices, the user can set the receive trigger level but not the transmit trigger level. The 654 provides ...
Page 17
Software Flow Control When software flow control is enabled, the 654 com- pares one or two sequential receive data characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the pro- grammed values, the 654 will ...
Page 18
ST16C654/654D current singular highest priority interrupt only. It could be noted that CTS and RTS interrupts have lowest interrupt priority. A condition can exist where a higher priority interrupt may mask the lower priority CTS/ RTS interrupt(s). Only after servicing ...
Page 19
XTAL1 and XTAL2 pins (see figure ). Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal baud rate generator for standard or ...
Page 20
ST16C654/654D Figure 11, Baud Rate Generator Circuitry Clock XTAL1 Oscillator XTAL2 Logic Rev. 4.10 MCR Bit-7=0 Divide by 1 logic Baudrate Generator Logic Divide by 4 logic MCR Bit-7=1 5-84 -BAUDOUT ...
Page 21
DMA Operation The 654 FIFO trigger level provides additional flexibil- ity to the user for block mode operation. LSR bits 5-6 provide an indication when the transmitter is empty or has an empty location(s). The user can optionally operate the ...
Page 22
ST16C654/654D Figure 12, INTERNAL LOOPBACK MODE DIAGRAM D0-D7 -IOR,-IOW RESET A0-A2 -CS A-D INT A-D -RXRDY -TXRDY XTAL1 XTAL2 Rev. 4.10 Transmit Transmit FIFO Shift Registers Register Flow Ir Control Encoder Logic Receive Receive FIFO Shift Registers Register Flow Ir ...
Page 23
REGISTER FUNCTIONAL DESCRIPTIONS The following table delineates the assigned bit functions for the fifteen 654 internal registers. The assigned bit functions are more fully defined in the following paragraphs. Table 6, ST16C654 INTERNAL REGISTERS Register BIT-7 [Default] ...
Page 24
ST16C654/654D Register BIT-7 [Note *5] Enhanced Register Set: Note * EFR[00] Auto CTS Xon-1[00] bit Xon-2[00] bit- Xoff-1[00] bit Xoff-2[00] bit-15 FIFO ...
Page 25
Transmit (THR) and Receive (RHR) Holding Reg- isters The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and Transmit Shift Register (TSR). The status of the THR is provided in the Line Status Register (LSR). Writing to ...
Page 26
ST16C654/654D Logic 0 = Disable the transmitter empty interrupt. (normal default condition) Logic 1 = Enable the transmitter empty interrupt. IER BIT-2: This interrupt will be issued whenever a fully as- sembled receive character is transferred from the RSR to ...
Page 27
Transmit operation in mode “0”: When the 654 is in the ST16C450 mode (FIFOs disabled, FCR bit-0 = logic the FIFO mode (FIFOs enabled, FCR bit-0 = logic 1, FCR bit-3 = logic 0) and when there ...
Page 28
ST16C654/654D Table 7, INTERRUPT SOURCE TABLE Priority [ ISR BITS ] Level Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit ...
Page 29
LCR BIT-3: Parity or no parity can be selected via this bit. Logic parity. (normal default condition) Logic parity bit is generated during the transmis- sion, receiver checks the data and parity for transmis- ...
Page 30
ST16C654/654D MCR BIT-5: Logic 0 = Disable Xon any function (for 16C550 compatibility). (normal default condition) Logic 1 = Enable Xon any function. In this mode any RX character received will enable Xon. MCR BIT-6: Logic 0 = Enable the ...
Page 31
FIFO data. This bit is cleared when LSR register is read. Modem Status Register (MSR) This register provides the current state of the control interface signals from the modem, or other peripheral device that ...
Page 32
ST16C654/654D Table 8, SOFTWARE FLOW CONTROL FUNCTIONS Cont-3 Cont-2 Cont ...
Page 33
Automatic RTS flow control is disabled. (normal default condition Enable Automatic RTS flow control. EFR bit-7: Automatic CTS Flow Control. Logic 0 = Automatic CTS flow control is disabled. (normal default ...
Page 34
ST16C654/654D AC ELECTRICAL CHARACTERISTICS T =0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified. A Symbol Parameter T T Clock pulse duration 1w Oscillator/Clock frequency 3w T Address ...
Page 35
AC ELECTRICAL CHARACTERISTICS T =0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified. A Symbol Parameter T Data setup time 33s T Data hold time 33h T Reset pulse width ...
Page 36
ST16C654/654D ABSOLUTE MAXIMUM RATINGS Supply range Voltage at any pin Operating temperature Storage temperature Package dissipation DC ELECTRICAL CHARACTERISTICS T =0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified. A ...
Page 37
A0-A4 T30s -CS R/-W T31d D0-D7 A0-A4 T30s -CS T32s R/-W D0-D7 Rev. 4.10 T30h T30w T31h General read timing in 68 mode T30h T32h T30w T33h T33s General write timing in 68 mode 5-101 ST16C654/654D T30d 8654-RD-1 T32d 8654-WD-1 ...
Page 38
ST16C654/654D A0-A2 Address T6s -CS T7d -IOR T12d D0-D7 A0-A2 Address T6s -CS T13d -IOW D0-D7 Rev. 4.10 Valid Active T7w T7h T9d Active T12h Data General write timing in 16 mode Valid Active T13h T13w T15d Active T16s T16h ...
Page 39
Active -IOW -RTS Change of state -DTR -CD -CTS -DSR INT -IOR -RI T2w EXTERNAL CLOCK Rev. 4.10 ST16C654/654D T17d Change of state Change of state T18d Active T19d Active Modem input/output timing T1w T3w External clock timing 5-103 Change ...
Page 40
ST16C654/654D START BIT RX INT -IOR Rev. 4.10 DATA BITS (5- DATA BITS 6 DATA BITS 7 DATA BITS 16 BAUD RATE CLOCK Receive timing 5-104 STOP BIT D6 D7 PARITY NEXT BIT ...
Page 41
START BIT RX -RXRDY -IOR Receive ready timing in none FIFO mode START BIT RX -RXRDY -IOR Rev. 4.10 ST16C654/654D DATA BITS (5- DATA BITS (5- Receive timing ...
Page 42
ST16C654/654D START BIT TX INT -IOW Active Rev. 4.10 DATA BITS (5- DATA BITS 6 DATA BITS 7 DATA BITS T23d 16 BAUD RATE CLOCK Transmit timing 5-106 STOP BIT D6 D7 PARITY ...
Page 43
START BIT TX -IOW Active D0-D7 BYTE #1 -TXRDY Transmit ready timing in none FIFO mode Rev. 4.10 ST16C654/654D DATA BITS (5- T27d Active Transmitter ready 5-107 STOP BIT D6 D7 PARITY NEXT BIT ...
Page 44
ST16C654/654D START BIT TX -IOW Active D0-D7 BYTE #64 T27d -TXRDY Transmit ready timing in FIFO mode Rev. 4.10 DATA BITS (5- DATA BITS 6 DATA BITS 7 DATA BITS T28d FIFO Full ...
Page 45
TX DATA IRTX (A-D) TX Bit Time IRRX (A-D) RX Bit Time RX DATA 0 Rev. 4.10 ST16C654/654D UART Frame Data Bits 3/16 Bit Time Infrared transmit timing ...
Page 46
Package Dimensions 100 LEAD PLASTIC QUAD FLAT PACK ( mm, QFP 100 Seating Plane A 1 1.6 mm Form INCHES MILLIMETERS SYMBOL MIN MAX MIN A 0.102 0.130 2.60 ...
Page 47
Package Dimensions 64 LEAD THIN QUAD FLAT PACK ( 1.4 mm, TQFP Seating Plane A 1 INCHES SYMBOL MIN A 0.055 A 0.002 1 A 0.053 2 B 0.005 ...
Page 48
Package Dimensions 68 LEAD PLASTIC LEADED CHIP CARRIER SYMBOL ...
Page 49
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im- prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de- scribed herein, conveys no ...