ST16C654CJ68 EXAR [Exar Corporation], ST16C654CJ68 Datasheet - Page 17

• Manufacturer Part Number: ST16C654CJ68
• Description: QUAD UART WITH 64-BYTE FIFO AND INFRARED (IrDA) ENCODER/DECODER
• Manufacturer: EXAR [Exar Corporation]

Software Flow Control
When software flow control is enabled, the 654 com-
pares one or two sequential receive data characters
with the programmed Xon or Xoff-1,2 character
value(s). If receive character(s) (RX) match the pro-
grammed values, the 654 will halt transmission (TX)
as soon as the current character(s) has completed
transmission. When a match occurs, the receive
ready (if enabled via Xoff IER bit-5) flags will be set
and the interrupt output pin (if receive interrupt is
enabled) will be activated. Following a suspension
due to a match of the Xoff characters values, the 654
will monitor the receive data stream for a match to the
Xon-1,2 character value(s). If a match is found, the
654 will resume operation and clear the flags (ISR bit-
4). The 654 offers a special Xon mode via MCR bit-5.
The initialized default setting of MCR bit-5 is a logic 0.
In this state Xoff and Xon will operate as defined
above. Setting MCR bit-5 to a logic 1 sets a special
operational mode for the Xon function. In this case
Xoff operates normally however, transmission (Xon)
will resume with the next character received, i.e., a
match is declared simply by the receipt of an incoming
(RX) character.
Reset initially sets the contents of the Xon/Xoff 8-bit
flow control registers to a logic 0. Following reset the
user can write any Xon/Xoff value desired for software
flow control. Different conditions can be set to detect
Xon/Xoff characters and suspend/resume transmis-
sions. When double 8-bit Xon/Xoff characters are
selected, the 654 compares two consecutive receive
characters with two software flow control 8-bit values
(Xon1, Xon2, Xoff1, Xoff2) and controls TX transmis-
sions accordingly. Under the above described flow
control mechanisms, flow control characters are not
placed (stacked) in the user accessible RX data buffer
or FIFO.
In the event that the receive buffer is overfilling and
flow control needs to be executed, the 654 automati-
cally sends an Xoff message (when enabled) via the
serial TX output to the remote modem. The 654 sends
the Xoff-1,2 characters as soon as received data
passes the programmed trigger level. To clear this
condition, the 654 will transmit the programmed Xon-
1,2 characters as soon as receive data drops below
Rev. 4.10
5-81
the programmed trigger level.
Special Feature Software Flow Control
A special feature is provided to detect an 8-bit charac-
ter when bit-5 is set in the Enhanced Feature Register
(EFR). When 8 bit character is detected, it will be
placed on the user accessible data stack along with
normal incoming RX data. This condition is selected in
conjunction with EFR bits 0-3. Note that software flow
control should be turned off when using this special
mode by setting EFR bit 0-3 to a logic 0.
The 654 compares each incoming receive character
with Xoff-2 data. If a match exists, the received data
will be transferred to FIFO and ISR bit-4 will be set to
indicate detection of special character (see Figure 9).
Although the Internal Register Table shows each X-
Register with eight bits of character information, the
actual number of bits is dependent on the pro-
grammed word length. Line Control Register (LCR)
bits 0-1 defines the number of character bits, i.e.,
either 5 bits, 6 bits, 7 bits, or 8 bits. The word length
selected by LCR bits 0-1 also determines the number
of bits that will be used for the special character
comparison. Bit-0 in the X-registers corresponds with
the LSB bit for the receive character.
Xon Any Feature
A special feature is provided to return the Xoff flow
control to the inactive state following its activation. In
this mode any RX character received will return the
Xoff flow control to the inactive state so that transmis-
sions may be resumed with a remote buffer. This
feature is more fully defined in the Software Flow
Control section.
Hardware/Software and Timeout Interrupts
Three special interrupts have been added to monitor
the hardware and software flow control. The interrupts
are enabled by IER bits 5-7. Care must be taken when
handling these interrupts. Following a reset the trans-
mitter interrupt is enabled, the 654 will issue an
interrupt to indicate that transmit holding register is
empty. This interrupt must be serviced prior to con-
tinuing operations. The LSR register provides the
ST16C654/654D