ST16C654CJ68 EXAR [Exar Corporation], ST16C654CJ68 Datasheet - Page 26

• Manufacturer Part Number: ST16C654CJ68
• Description: QUAD UART WITH 64-BYTE FIFO AND INFRARED (IrDA) ENCODER/DECODER
• Manufacturer: EXAR [Exar Corporation]

ST16C654/654D
Logic 0 = Disable the transmitter empty interrupt.
(normal default condition)
Logic 1 = Enable the transmitter empty interrupt.
IER BIT-2:
This interrupt will be issued whenever a fully as-
sembled receive character is transferred from the
RSR to the RHR/FIFO, i.e., data ready, LSR bit-0.
Logic 0 = Disable the receiver line status interrupt.
(normal default condition)
Logic 1 = Enable the receiver line status interrupt.
IER BIT-3:
Logic 0 = Disable the modem status register interrupt.
(normal default condition)
Logic 1 = Enable the modem status register interrupt.
IER BIT -4:
Logic 0 = Disable sleep mode. (normal default condi-
tion)
Logic 1 = Enable sleep mode. See Sleep Mode section
for details.
IER BIT-5:
Logic 0 = Disable the software flow control, receive
Xoff interrupt. (normal default condition)
Logic 1 = Enable the software flow control, receive
Xoff interrupt. See Software Flow Control section for
details.
IER BIT-6:
Logic 0 = Disable the RTS interrupt. (normal default
condition)
Logic 1 = Enable the RTS interrupt. The 654 issues an
interrupt when the RTS pin transitions from a logic 0
to a logic 1.
IER BIT-7:
Logic 0 = Disable the CTS interrupt. (normal default
condition)
Logic 1 = Enable the CTS interrupt. The 654 issues an
interrupt when CTS pin transitions from a logic 0 to a
logic 1.
FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the
FIFOs, set the transmit/receive FIFO trigger levels,
and select the DMA mode. The DMA, and FIFO
modes are defined as follows:
Rev. 4.10
5-90
DMA MODE
single transmit or receive operation, and is similar to
the ST16C454 mode. Transmit Ready (-TXRDY) will
go to a logic 0 when ever an empty transmit space is
available in the Transmit Holding Register (THR).
Receive Ready (-RXRDY) will go to a logic 0 when-
ever the Receive Holding Register (RHR) is loaded
with a character.
mode operation. The transmit interrupt is set when the
transmit FIFO is below the programmed trigger level.
-TXRDY remains a logic 0 as long as one empty FIFO
location is available. The receive interrupt is set when
the receive FIFO fills to the programmed trigger level.
However the FIFO continues to fill regardless of the
programmed level until the FIFO is full. -RXRDY
remains a logic 0 as long as the FIFO fill level is above
the programmed trigger level.
FCR BIT-0:
Logic 0 = Disable the transmit and receive FIFO.
(normal default condition)
Logic 1 = Enable the transmit and receive FIFO. This
bit must be a “1” when other FCR bits are written to or
they will not be programmed.
FCR BIT-1:
Logic 0 = No FIFO receive reset. (normal default
condition)
Logic 1 = Clears the contents of the receive FIFO and
resets the FIFO counter logic (the receive shift regis-
ter is not cleared or altered). This bit will return to a
logic 0 after clearing the FIFO.
FCR BIT-2:
Logic 0 = No FIFO transmit reset. (normal default
condition)
Logic 1 = Clears the contents of the transmit FIFO and
resets the FIFO counter logic (the transmit shift regis-
ter is not cleared or altered). This bit will return to a
logic 0 after clearing the FIFO.
FCR BIT-3:
Logic 0 = Set DMA mode “0”. (normal default condi-
tion)
Logic 1 = Set DMA mode “1.”
Mode 0
Mode 1
Set and enable the interrupt for each
Set and enable the interrupt in a block