ST16C654CJ68 EXAR [Exar Corporation], ST16C654CJ68 Datasheet - Page 15
ST16C654CJ68
Manufacturer Part Number
ST16C654CJ68
Description
QUAD UART WITH 64-BYTE FIFO AND INFRARED (IrDA) ENCODER/DECODER
Manufacturer
EXAR [Exar Corporation]
Datasheet
1.ST16C654CJ68.pdf
(49 pages)
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Note *2: These registers are accessible only when LCR bit-7 is set to a logic 1.
Note *3: Enhanced Feature Register, Xon 1,2 and Xoff 1,2 are accessible only when the LCR is set to
“BF(HEX).
Note *4: FIFO Ready Register is available through the CSRDY interface pin only.
Rev. 4.10
A2
X
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
General Register Set (THR/RHR, IER/ISR, MCR/MSR, LCR/LSR, SPR):
Baud Rate Register Set (DLL/DLM): Note *2
Enhanced Register Set (EFR, Xon/off 1-2): Note *3
FIFO Ready Register: Note *4
A1
X
0
0
1
1
0
0
1
1
0
0
1
0
0
1
1
A0
X
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
Table 4, INTERNAL REGISTER DECODE
READ MODE
Receive Holding Register
Interrupt Status Register
Line Status Register
Modem Status Register
Scratchpad Register
LSB of Divisor Latch
MSB of Divisor Latch
Enhanced Feature Register
Xon-1 Word
Xon-2 Word
Xoff-1 Word
Xoff-2 Word
RXRDY (A-D), TXRDY (A-D)
5-79
WRITE MODE
Transmit Holding Register
Interrupt Enable Register
FIFO Control Register
Line Control Register
Modem Control Register
Scratchpad Register
LSB of Divisor Latch
MSB of Divisor Latch
Enhanced Feature Register
Xon-1 Word
Xon-2 Word
Xoff-1 Word
Xoff-2 Word
ST16C654/654D