PSMN9R0-30YL_10 NXP [NXP Semiconductors], PSMN9R0-30YL_10 Datasheet - Page 8

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PSMN9R0-30YL_10

Manufacturer Part Number
PSMN9R0-30YL_10
Description
N-channel TrenchMOS logic level FET
Manufacturer
NXP [NXP Semiconductors]
Datasheet
NXP Semiconductors
PSMN9R0-30YL_3
Product data sheet
Fig 13. Normalized drain-source on-state resistance
Fig 15. Gate-source voltage as a function of gate
a
V
1.5
0.5
(V)
10
GS
2
1
0
8
6
4
2
0
−60
factor as a function of junction temperature
charge; typical values
0
0
V
5
DS
= 12 (V)
60
10
V
120
DS
15
= 19 (V)
All information provided in this document is subject to legal disclaimers.
Q
003aac540
T
G
j
( ° C)
(nC)
03aa27
180
20
Rev. 03 — 5 January 2010
Fig 14. Gate charge waveform definitions
Fig 16. Input, output and reverse transfer capacitances
(pF)
C
1400
1200
1000
800
600
400
200
0
10
as a function of drain-source voltage; typical
values
V
-1
V
V
V
GS(pl)
DS
GS(th)
GS
C
C
C
rss
iss
oss
N-channel TrenchMOS logic level FET
Q
GS1
1
I
Q
PSMN9R0-30YL
D
GS
Q
GS2
Q
G(tot)
Q
GD
10
© NXP B.V. 2010. All rights reserved.
V
DS
003aaa508
003aac543
(V)
10
2
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