LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 153

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

DREQ
DACK
Register: 0x1B (0x9B)
Chip Test Three (CTEST3)
Read/Write
V[3:0]
FLF
CLF
7
x
x
Data Request Status
This bit indicates the status of the LSI53C875’s internal
Data Request signal (DREQ). When this bit is set, DREQ
is active. When this bit is clear, DREQ is inactive.
Data Acknowledge Status
This bit indicates the status of the LSI53C875’s internal
Data Acknowledge signal (DACK/). When this bit is set,
DACK/ is inactive. When this bit is clear, DACK/ is active.
Chip revision level
These bits identify the chip revision level for software
purposes. The value should be the same as the lower
nibble of the PCI
configuration space.
Flush DMA FIFO
When this bit is set, data residing in the DMA FIFO is
transferred to memory, starting at the address in the
Next Address (DNAD)
signal, controlled by the
register, determines the direction of the transfer. This bit
is not self-clearing; clear it once the data is successfully
transferred by the LSI53C875. Polling of FIFO flags is
allowed during flush operations.
Clear DMA FIFO
When this bit is set, all data pointers for the DMA FIFO
are cleared. Any data in the FIFO is lost. After the
LSI53C875 successfully clears the appropriate FIFO
pointers and registers, this bit automatically clears. This
bit does not clear the data visible at the bottom of the
FIFO.
V
x
4
x
Revision ID
register. The internal DMAWR
FLF
3
0
Chip Test Five (CTEST5)
register, at address 0x08 in
CLF
2
0
FM
1
0
WRIE
DMA
0
0
[7:4]
5-37
1
0
3
2