LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 74

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

Burst Size Selection – The Read Multiple command reads in multiple
cache lines of data in a single bus ownership. The number of cache lines
to be read is a multiple of the cache line size specified in Revision 2.1
of the PCI specification. The logic selects the largest multiple of the
cache line size based on the amount of data to transfer, with the
maximum allowable burst size being determined from the
DMA Mode
(DMODE)
burst size bits and
Chip Test Five
(CTEST5), bit 2.
Read Multiple with Read Line Enabled – When both the Read
Multiple and Read Line modes are enabled, the Read Line command is
not issued if the above conditions are met. Instead, a Read Multiple
command is issued, even though the conditions for Read Line are met.
If the Read Multiple mode is enabled and the Read Line mode is
disabled, Read Multiple commands are issued if the Read Multiple
conditions are met.
Unsupported PCI Commands – The LSI53C875 does not respond to
reserved commands, special cycle, dual address cycle, or interrupt
acknowledge commands as a slave. It never generates these commands
as a master.
3-10
PCI Functional Description