LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 50

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

2.5.11.1 Determining the Data Transfer Rate
Figure 2.5
2.5.11.2
2-26
CCF2
SCLK
0
0
0
1
0
1
CCF1
SCSI Control Three (SCNTL3)
0
1
1
0
0
0
SCF2
0
0
0
1
0
1
Determining the Synchronous Transfer Rate
Doubler
Clock
CCF0
1
0
1
0
0
1
SCF1
Synchronous data transfer rates are controlled by bits in two different
registers of the LSI53C875. Following is a brief description of the bits.
Figure 2.5
the role of the register bits in determining the transfer rate.
The SCF[2:0] bits select the factor by which the frequency of SCLK is
divided before being presented to the synchronous SCSI control logic.
The output from this divider controls the rate at which data can be
received; this rate must not exceed 80 MHz. The receive rate of
synchronous SCSI data is one-fourth of the SCF divider output. For
Functional Description
0
1
1
0
0
0
Divisor
1.5
1
2
3
3
4
SCF0
1
0
1
0
0
1
illustrates the clock division factors used in each register, and
Divisor
SCF
1.5
1
2
3
3
4
Divider
Divider
Register, Bits [6:4] (SCF[2:0])
SCF
CCF
This point
must not
80 MHz
exceed
Example (8-bit SCSI bus):
SCLK = 80 MHz, SCF = 1 (
CCF = 5 ( 4)
SCSI send rate = (SCLK
= (80
SCSI receive rate = (SCLK
= (80
This point
must not
25 MHz
exceed
TP2
1)
1)
0
0
0
0
1
1
1
1
Asynchronous
Divide by 4
Synchronous
4 = 20 Mbytes/s
4 = 20 Mbytes/s
SCSI Logic
Divider
TP1
0
0
1
1
0
0
1
1
SCF)
TP0
SCF)
0
1
0
1
0
1
0
1
, XFERP = 4 ( 4),
(to SCSI Bus)
Send Clock
XFERP
Receive
Clock
4
XFERP
Divisor
4
5
6
7
8
9
10
11