Z80182 Zilog., Z80182 Datasheet
Z80182
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Z80182 Summary of contents
Page 1
... In external applications, three 8-bit parallel ports are available for driving LEDs or other devices. Figure 1 shows the Z80182/ Z8L182 block diagram, while the pin assignments for the QFP and the VQFP packages are shown in Figures 2 and 3, respectively ...
Page 2
... Z180 Signals or Port B Note: Conventional use of the term "MPU side" refers to all interface through the Z180 MPU core and "PC side" refers to all interface through the16550 MIMIC interface. Figure 1. Z80182/Z8L182 Functional Block Diagram 3 Z8S180 (Static Z80180) ...
Page 3
... A9 A10 15 A11 A12 VSS A13 A14 20 A15 A16 A17 A18/TOUT VDD 25 A19 Figure 2. Z80182/Z8L182 100-Pin QFP Pin Configuration DS971820600 Z80182/Z8L182 100-Pin QFP Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL 80 /TRXCB/HA0 TXDB//HDDIS /CTSB//HWR ...
Page 4
... E 85 /M1 /WR /RD PHI VSS 90 XTAL EXTAL /WAIT /BUSACK /BUSREQ 95 /RESET /NMI /INT0 /INT1/PC6 /INT2/PC7 100 1 Figure 3. Z80182/Z8L182 100-Pin VQFP Pin Configuration 3 Z80182/Z8L182 100-Pin VQFP Z80182/Z8L182 Z I ILOG NTELLIGENT EV1 /ROMCS /RAMCS ...
Page 5
... This signal will stop the CPU from executing further instructions and places the address/data buses and other control signals, into the high impedance state. Z80182/Z8L182 ILOG NTELLIGENT ...
Page 6
... RxA1. Received Data ASCI channel 1 (input, active High). This pin is multiplexed with PB6 (parallel Port B, bit 6) on the RxA1/PB6 pin. TxA1. Transmitted Data ASCI Channel 1 (output, active High). This pin is multiplexed with PB5 (parallel Port B, bit 5) on the TxA1/PB5 pin. Z80182/Z8L182 ILOG NTELLIGENT ...
Page 7
... TxDB. Transmit Data (output, active High). This output signal transmits channel B’s serial data at standard TTL levels. In Z80182/Z8L182 mode 1, TxDB is multiplexed with the 16550 MIMIC interface /HDDIS signal on the TxDB//HDDIS pin. RxDA. Receive Data (inputs, active High). These inputs receive channel A’ ...
Page 8
... In SDLC mode, these pins act as outputs and are valid on receipt of a flag. In Z80182/Z8L182 mode 1 the /SYNCB signal is multiplexed with the 16550 MIMIC interface /HCS input on the /SYNCB //HCS pin. ...
Page 9
... Host Receive Ready (output, active Low). In Z80182/Z8L182 mode 1, this output is used by the 16550 MIMIC interface in DMA mode to signal the PC/XT/AT that a data byte is ready in the Receive Buffer. In Z80182/ Z8L182 mode 0, this pin is multiplexed with the ESCC /RTSB signal and the Z180 MPU /TEND1 signal on the /TEND1/RTSB /HRxRDY pin ...
Page 10
... If divide-by-one mode is enabled, the PHI frequency is equivalent to that of crystal or input frequency. The PHI frequency is also fed to the ESCC core. If running over 20 MHz (5V MHz (3V) the PHI-ESCC frequency divider should be enabled to divide the PHI clock by two prior to feeding into the ESCC core. Z80182/Z8L182 ILOG NTELLIGENT ...
Page 11
... The pins below are multiplexed based upon the value of bit 1 of the System Configuration register. If bit then the Z80182/Z8L182 Mode 0 (non-16550 MIMIC mode) signals are selected; if bit then Z80182/Z8L182 Mode 1 (16550 MIMIC mode) signals are selected. On Reset, Z80182/Z8L182 Mode 0 is always selected as shown in Table 3 ...
Page 12
... Z180 Note 2: Interrupt Edge /Pin MUX register, bit 3 chooses between the /MWR or PC2//RTSA combination; the System Configuration Register bit 7 chooses between PC2 and /RTSA. Refer to Table 5 for the 1st, 2nd and 3rd pin functions. Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL ™ ...
Page 13
... 2nd 3rd Function Function PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL MUX Control SYS CONF REG Bit 5 SYS CONF REG Bit 5 SYS CONF REG Bit 5 SYS CONF REG Bit 5 SYS CONF REG Bit 5 ...
Page 14
... HD2 HD3 HD4 HD5 HD6 HD7 PC5 PC3 PC2 RTSA PC1 PC0 PC4 IEO Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL MUX Control SYS CONF REG Bit 1,2 SYS CONF REG Bit 1,2 SYS CONF REG Bit 1,2 SYS CONF REG Bit 1 SYS CONF REG Bit 1 ...
Page 15
... Function Function /HRD /HWR /HDDIS HA0 HA1 HA2 /HCS /MREQ PC6** PC7** Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL MUX Control SYS CONF REG Bit 1 SYS CONF REG Bit 1 SYS CONF REG Bit 1 SYS CONF REG Bit 1 SYS CONF REG Bit 1 ...
Page 16
... Zilog Z80182/Z8L182 FUNCTIONAL DESCRIPTION Functionally, the on-chip Z182 MPU and ESCC same as the discrete devices (Figure 1). Therefore, for a detailed description of each individual unit, refer to the Z182 MPU FUNCTIONAL DESCRIPTION This unit provides all the capabilities and pins of the Zilog Z8S180 MPU (Static Z80180 MPU). Figure 4 shows the S180 MPU Block Diagram of the Z182. This allows 100% Timing & ...
Page 17
... I/O cycles. This unit also inserts wait states during on- chip DMA transactions. When using RAMCS and ROMCS wait state generators, the wait state controller with the most programmed wait states will determine the number of wait states inserted. Z80182/Z8L182 ILOG NTELLIGENT ...
Page 18
... New programmable features added with Write Register 7' (WR seven prime) Write registers and 10 are now readable Read register 0 latched during access DPLL counter output available as jitter-free transmitter clock source Enhanced /DTR, /RTS deactivation timing Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL DS971820600 ...
Page 19
... Z80182/Z8L182 only: New 32-bit CRC-32 (Ethernet Polynomial) ESCC Programmable Clock - programmed to be equal to system clock divided by one or two - programmed by Z80182 Enhancement Register Note: The ESCC programmed to divide-by-two mode when operating above the following conditions: – PHI > 20 MHz at 5.0V – PHI > 10 MHz at 3.0V ...
Page 20
... Data Decode & SDLC Frame Status FIFO Sync Character Detection * 8 bytes each Internal Channel A Control Register Logic Interrupt Channel B Control Register Logic Figure 5. ESCC Block Diagram Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL TxDA /TRxCA /RTxCA /CTSA /DCDA /SYNCA /RTSA /DTRA//REQA RxDA Channel A ...
Page 21
... Control of the register set is maintained by six priority encoded interrupts to the Z80182/Z8L182. When the PC/ XT/AT writes to THR, MCR, LCR, DLL, DLM, FCR or reads the RBR, an interrupt to the Z80182/Z8L182 is generated. Each interrupt can be individually masked off or all interrupts can be disabled by writing a single bit. Both mode 0 and mode 2 interrupts are supported by the 16550 MIMIC interface ...
Page 22
... See Table 6 for the setting and clearing of the Line Status Register bits 16x8 R Data Bits Write ALU Pointer Z80182/Z8L182 Z I ILOG NTELLIGENT error PC Read 3 LSR B2-B4 Internal Clock R 16x3 E Error A Bits D Sync B ...
Page 23
... MPU writes 1 MPU writes 1 MPU writes 1 MPU makes two writes to receiver buffer register MPU writes to RCVR FIFO or receiver buffer register Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL How to Clear When there are no more errors MPU writes a 0 When holding register ...
Page 24
... E R Data Bits Write Read ALU Pointer Pointer Z80182/Z8L182 ILOG NTELLIGENT Internal Clock I Sync PC Cntrl Line 8 PC Side Databus (PC Side Write) Internal Clock PC IRQ 16550 MIMIC or PC Side Interface DS971820600 ERIPHERAL ...
Page 25
... MPU FSCR control register (MPU write only xxECH) bits 6 and 7. A timeout feature exists, Transmit Timeout Timer, Z80182/Z8L182 MIMIC SYNCHRONIZATION CONSIDERATIONS Because of the asynchronous nature of the FIFO’s on the MIMIC, some synchronization plan must be provided to prevent conflict from the dual port accesses of the MPU and the PC ...
Page 26
... The PC THRE bit in the LSR Register is set when the THR Register is empty Host writes to the 16450 THR Register; 3. Whenever the Z80182 TSR buffer is empty and one character delay timer timed-out state, the byte from the THR Register is transferred to the TSR buffer; ...
Page 27
... Zilog PARALLEL PORTS FUNCTIONAL DESCRIPTION The Z80182/Z8L182 has three 8-bit bi-directional Ports. Each bit is individually programmable for input or output (with the exception of PC6 and PC7 which are inputs only). PROGRAMMING The following subsections explain and define the parameters for I/O Address assignments. The three tables in this section describe the mapping of the common registers shared by the MPU and the 16550 MIMIC ...
Page 28
... Zilog PROGRAMMING (Continued) Table 9. Z80182/Z8L182 ESCC, PIA and MISC Registers Register Name WSG Chip Select Register Z80182 Enhancements Register PC Data Direction Register PC Data Register Interrupt Edge/Pin MUX Control ESCC Chan A Control Register ESCC Chan A Data Register ESCC Chan B Control Register ESCC Chan B Data Register ...
Page 29
... Zilog Z182 MPU CONTROL REGISTERS Figures 10 through 50 refer to the Z80182/Z8L182 MPU Control registers. For additional information, refer to the Z8S180 Product Specification and Technical Manual. ASCI CHANNELS CONTROL REGISTERS CNTLA0 MPE Bit RE Upon RESET 0 0 R/W R/W R/W DS971820600 Addr 00H ...
Page 30
... Start + 8-Bit Data + Parity + 1 Stop Start + 8-Bit Data + Parity + 2 Stop Figure 10b. ASCI Control Register A (Ch ILOG NTELLIGENT MODE Selection Read - Multiprocessor Bit Receive Write - Error Flag Reset CKA1 Disable Transmit Enable Receive Enable Multiprocessor Enable DS971820600 Z80182/Z8L182 P ERIPHERAL ...
Page 31
... Figure 11. ASCI Control Register B (Ch. 0) Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL Clock Source and Speed Select Divide Ratio Parity Even or Odd Clear To Send/Prescale Multiprocessor Multiprocessor Bit Transmit (Divide Ratio = 30) ...
Page 32
... Figure 12. ASCI Control Register B (Ch. 1) Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL Clock Source and Speed Select Divide Ratio Parity Even or Odd Read - Status of /CTS pin Write - Select PS Multiprocessor Multiprocessor Bit Transmit ...
Page 33
... Data Carrier Detect Receive Interrupt Enable Framing Error Parity Error Over Run Error Receive Data Register Full Transmit Interrupt Enable Transmit Data Register Empty /CTS1 Enable Receive Interrupt Enable Framing Error Parity Error Over Run Error Receive Data Register Full Z80182/Z8L182 P ERIPHERAL 3-33 ...
Page 34
... Figure 18. ASCI Receive Data Register (Ch. 1) BRK0 Read/Write Figure 19. ASCI Break Control Register (Ch. 0) BRK1 Read/Write Figure 20. ASCI Break Control Register (Ch. 1) Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL Addr 09H Received Data Addr 12H ...
Page 35
... Addr 0BH Read - Received Data Write - Transmit Data Z I ILOG NTELLIGENT SS0 1 R/W Speed Select Transmit Enable Receive Enable End Interrupt Enable End Flag Baud Rate Ø 320 Ø 640 Ø 1280 External Clock (Frequency < Ø Z80182/Z8L182 P ERIPHERAL 20) 3-35 ...
Page 36
... When Read, read Data Register L before reading Data Register H. Figure 26. Timer 1 Data Register H RLDR0H Read/Write Figure 29. Timer 0 Reload Register H RLDR1H Read/Write Figure 30. Timer 1 Reload Register H Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL Addr 0DH 8 Addr 15H 8 ...
Page 37
... Addr 10H TIE1 TIE0 TOC1 TOC0 TDE1 TDE0 R/W R/W R/W R/W R/W R/W Inhibited Toggle 0 1 Figure 31. Timer Control Register Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL Timer Down Count Enable 1,0 Timer Output Control 1,0 Timer Interrupt Enable 1,0 Timer Interrupt Flag 1,0 3-37 ...
Page 38
... Bits 0-2 (3) are used for SAR0B A19, A18, A17, A16 DMA Transfer Request /DREQ0 (external RDR0 (ASCI0 RDR1 (ASCI1 Not Used Figure 34. DMA 0 Source Address Registers Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL DS971820600 ...
Page 39
... Figure 37. DMA 1 Memory Address Registers IAR1L Read/Write IA7 IAR1H Read/Write IA15 Figure 38. DMA I/O Address Registers BCR1L Read/Write BC7 BCR1H Read/Write BC15 Figure 39. DMA 1 Byte Count Registers Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL Addr 28H MA0 Addr 29H MA8 Addr 2AH MA19 MA16 - ...
Page 40
... M DAR0 DAR0 Fixed 10 M DAR0 Fixed 11 I/O Figure 41. DMA Mode Registers Z80182/Z8L182 Z I ILOG NTELLIGENT DMA Master Enable DMA Interrupt Enable 1, 0 DMA Enable Bit Write Enable 1, 0 DMA Enable Memory MODE Select Ch 0 Source Mode Destination Mode 1, 0 ...
Page 41
... Address Increment/Decrement M - I/O MAR1 I/O MAR1-1 I IAR1 Fixed I IAR1 Fixed Figure 42. DMA/WAIT Control Register Z I ILOG NTELLIGENT Addr 32H DIM0 0 R/W DMA Ch 1 I/O Memory Mode Select /DREQi Select I/0 Wait Insertion Memory Wait Insertion IAR1 Fixed IAR1 Fixed MAR1+1 MAR1-1 Z80182/Z8L182 P ERIPHERAL 3-41 ...
Page 42
... R/W R/W R/W R/W R/W Figure 44. MMU Bank Base Register Addr 3AH CA1 CA0 BA3 BA2 BA1 BA0 R/W R/W R/W R/W R/W R/W Z80182/Z8L182 Z I ILOG NTELLIGENT CB0 0 R/W MMU Common Base Register BB0 0 R/W MMU Bank Base Register 0 MMU Bank Area Register MMU Common Area Register DS971820600 P ERIPHERAL ...
Page 43
... CYC1 CYC0 R/W Interval of Refresh Cycle 10 states 20 states 40 states 80 states Figure 48. Refresh Control Register Z I ILOG NTELLIGENT Addr 33H - 0 Interrupt Vector Low Addr 34H ITE0 1 R/W /INT Enable Undefined Fetch Object TRAP 0 R/W Cycle Select Refresh Wait State Refresh Enable Z80182/Z8L182 P ERIPHERAL 3-43 ...
Page 44
... Upon Reset R/W R/W R/W R/W 3- Addr 3EH - - - - - Figure 49. Operation Mode Control Register Addr 3FH - - - - - Figure 50. I/O Control Register Z80182/Z8L182 Z I ILOG NTELLIGENT I/O Compatibility /M1 T emporary Enable /M1 Enable I/O Stop I/O Address Combination reserved DS971820600 P ERIPHERAL ...
Page 45
... The clocking is resumed within the Z8S180 and at the system clock output after /RESET is asserted when the crystal oscillator is restarted, but not yet stabilized. Z80182/Z8L182 ILOG NTELLIGENT ...
Page 46
... Low. IDLE Mode IDLE mode is another power-down mode offered by the Z8S180. To enter IDLE mode: 1. Set D6 and and 1, respectively. 2. Set the I/O STOP bit (D5 of ICR, I/O Address = 3FH Execute the SLEEP instruction. Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL DS971820600 ...
Page 47
... EMI noise generated by the part. CPU Control Register (CCR) Addr 1FH Figure 51. CPU Control Register Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL LNAD/DATA 0 = Standard Drive 1 = 25% Drive On A19-A0, D7-D0 LNCPUCTL 0 = Standard Drive ...
Page 48
... E Bit 0. LNAD/DATA. This bit controls the drive capability of the Address/Data bus output drivers. If this bit is set to 1, the output drive capability of the Address and Data bus output is reduced to 25% of its original drive capability. Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL - /MREQ ...
Page 49
... See Figures 52 and 53 for the ESCC Control registers. For additional information, refer to the ESCC Product Specification /Technical Manual. The Z80182/Z8L182 has two ESCC channels. They can be accessed in any page of I/O space since only the lowest eight address lines are decoded for access. Their Z180 MPU Address locations are shown in Table 11 ...
Page 50
... Note: The ESCC cannot do simultaneous calculation/ comparison using both 16-bit and 32-bit CRC. Also, for the Z80182/Z8L182 only, the clock provided to the ESCC core is equal to the system clock divided The divider is programmed in the Z80182 Enhancement Register bit 3. ...
Page 51
... X1 Clock Mode 0 1 X16 Clock Mode 1 0 X32 Clock Mode 1 1 X64 Clock Mode Figure 52. Write Register Bit Functions Z80182/Z8L182 Z I ILOG NTELLIGENT Interrupt Vector Enable Sync Character Load Inhibit Address Search Mode (SDLC) ...
Page 52
... Sync9 Sync8 Sync7 Sync6 Sync5 ILOG NTELLIGENT Sync0 Monosync, 8 Bits Sync0 Monosync, 6 Bits Sync0 Bisync, 16 Bits 1 Bisync, 12 Bits ADR0 SDLC x SDLC (Address Range) Sync0 Monosync, 8 Bits x Monosync, 6 Bits Sync8 Bisync, 16 Bits Sync4 Bisync, 12 Bits 0 SDLC DS971820600 Z80182/Z8L182 P ERIPHERAL ...
Page 53
... Transmit Clock = /RTxC Pin 0 1 Transmit Clock = /TRxC Pin 1 0 Transmit Clock = BR Generator Output 1 1 Transmit Clock = DPLL Output 0 Receive Clock = /RTxC Pin 1 Receive Clock = /TRxC Pin 0 Receive Clock = BR Generator Output 1 Receive Clock = DPLL Output /RTxC Xtal//No Xtal Z80182/Z8L182 P ERIPHERAL 3-53 ...
Page 54
... Local Loopback 0 Null Command 1 Enter Search Mode 0 Reset Missing Clock 1 Disable DPLL 0 Set Source = BR Generator 1 Set Source = /RTxC 0 Set FM Mode 1 Set NRZI Mode WR7' SDLC Feature Enable Zero Count IE SDLC FIFO Enable DCD IE Sync/Hunt IE CTS IE Tx Underrun/EOM IE Break/Abort IE DS971820600 Z80182/Z8L182 P ERIPHERAL ...
Page 55
... Read Register Interrupt V3 Vector *Can only be accessed if the SDLC FIFO enhancement is enabled (WR15 bit D2 set to 1) SDLC FIFO Status and Byte Count (LSB) Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL Ext/Status ...
Page 56
... Loop 0 0 Loop Sending 0 Two Clocks Missing One Clock Missing Read Register Lower Byte of Time Constant Figure 53. Read Register Bit Functions Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL TC8 TC9 TC10 TC11 Upper Byte of Time Constant TC12 ...
Page 57
... When this bit is set to 1, the Z182 is in “ROM emulator mode”. In this mode, bus direction for certain transaction periods are set to the opposite direction to export internal bus transactions outside the Z80182/Z8L182. This allows the use of ROM emulators/logic analyzers for application development (see Tables 12a and 12b). ...
Page 58
... Z80182 In Out /Z8L182 Data Bus DD =0) OUT Z80182 In Out /Z8L182 Data Bus (DD =1) OUT Table 13b. Data Bus Direction (Z80182/Z8L182 is not Bus Master) Interrupt Acknowledge Transaction Intack For On-Chip Peripheral Z80182/Z8L182 Data Bus (DD =0) OUT Z80182/Z8L182 Data Bus (DD =1) OUT 3- ...
Page 59
... ROM boundary set by the ROMBR register will cause the ROMCS pin to go Low. Bit 2 Tri-Muxed Pins Select The Z80182/Z8L182 has three pins that are triple multiplexed and controlled by bit 2 and bit 1. Table 14 shows the different modes. Table 14. SCR Control for Triple Multiplexed Pins ...
Page 60
... RAM lower boundary address (RAMLBR register) = 0FFFFFH RAM upper boundary address (RAMUBR register) = 0FFFFFH Z80182 Improvement to the Wait State Generator A separate Wait State Generator is provided for access memory using /ROMCS and /RAMCS. A single 8-bit register is added to enable/disable this feature as well as provide two 3-bit fields that provide waits for each chip select ...
Page 61
... CKS - RxS/CTS1 - TxS Programming this bit to 0 selects normal drive for the Z182 pins. Refer to the Z8S180 Product Specification for Low noise control of Z180 pins. Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL - CKA1/TEND0 - CKA0/DREQ0 ...
Page 62
... After the first memory access, the wait states will be inserted as programmed in the wait state generators. In addition, if bit 4 of the Z80182 Enhancement Register is set, the TxDA pin will be tri-stated during Halt and Recovery modes. Z80182/Z8L182 ...
Page 63
... High with only the pull-up of the HINTR pin driving; otherwise this pin is tri-state. Wired AND is needed when an external arbiter is not available. 0 HINTR is driven when out 2 of the Modem Control Register is 1. HINTR is tri-state when MCR out RESERVED Z80182/Z8L182 P ERIPHERAL 3-63 ...
Page 64
... Z180. Bit 0 FIFO Control Register Write (Read Only) This bit is set when the PC/XT/AT writes to the FCR. This bit is also set when Transmit occurs reset when the Z180 MPU reads this register. Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL ™ ...
Page 65
... These three bits are the Interrupt Status bits when VIS in the MMC register is 1 (Z180 Interrupt Mode 2). If VIS bit is 0, then this field contains bit 3-bit 1 of the opcode. If the VIS bit is 0, then these bits contain what was last written to them. Z80182/Z8L182 ILOG ...
Page 66
... PC trigger level. If this timer reaches zero, an interrupt is sent to the PC. Bit 4 Transmitter Timeout Enable This bit enables the Z80182/Z8L182 timer that is used to interrupt the Z180 MPU if characters are available, but are below the trigger level. The timer is enabled to count down if this bit is 1 and the number of bytes is below the set transmitter trigger level ...
Page 67
... The output of the BRG should be routed to the /TRxCB pin Figure 67. Transmitter Time Constant Register (Z180 MPU Read/Write, Address xxFAH) Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL ™ MPU and the PC/XT/AT, two 1 ...
Page 68
... PC will not see data requests from an empty FIFO any faster than would occur with a true UART when the delay feature is enabled. This timer is also used to delay data transfer for TSR buffer to Z80182 THR in double buffer mode. 3- ...
Page 69
... Zilog 16550 MIMIC REGISTERS The Z80182/Z8L182 contains the following set of registers for interfacing with the PC/XT/AT. – Receive Buffer Register – Transmit Holding Register – Interrupt Enable Register – Interrupt Identification Register – FIFO Control Register – Line Control Register – Modem Control Register – ...
Page 70
... When disabled, the internal MIMIC IEO becomes deasserted only after an interrupt acknowledge cycle. In this case possible for the ESCC to force it's interrupt vector onto the data bus even when the MIMIC has a pending interrupt and is higher in priority. Z80182/Z8L182 ILOG NTELLIGENT ...
Page 71
... Table 19. Interrupt Identification Field Interrupt Source Overrun, Parity, Framing error or Break detect bits set by MPU Received Data trigger level Receiver Timeout with data in RCVR FIFO. Transmitter Holding Register Empty. MODEM status: CTS, DSR DCD Z80182/Z8L182 Z I ILOG NTELLIGENT ...
Page 72
... If bit 5 of the LSR is set and this enable bit is a logic 1, then an interrupt to the PC is generated. Bit 0 Received Data Available IRQ If bit 0 of the LSR is set or a Receive Timeout occurs and this enable bit is a logic 1, then an interrupt to the PC is generated. Z80182/Z8L182 ILOG NTELLIGENT ...
Page 73
... If an access is made to address 1, the Divisor Latch Most Significant byte is accessed. Bit 6 - Bit 0 These bits do not affect the Z80182/Z8L182 directly, however they can be read by the Z180 MPU and the 16550 MIMIC modes can be emulated by the Z180 MPU ...
Page 74
... Writing to this register with the PC/XT/AT will generate an interrupt to the Z180 MPU. It can then read the Baud rate divisor and set up the application ILOG NTELLIGENT Divisor Latch (MS) Figure 80. Divisor Latch (LS Scratch Register Figure 81. Divisor Latch (MS) DS971820600 Z80182/Z8L182 P ERIPHERAL ...
Page 75
... Z180 core's PHI clock output. Note: If operating above 20 MHz/ MHz/3V, this bit should be set for ESCC divide-by-two mode Figure 82. Z80182 Enhancements Register (Z180 MPU Read/Write, Address xxD9H) Z80182/Z8L182 ILOG NTELLIGENT ...
Page 76
... Zilog PARALLEL PORTS REGISTERS The Z80182/Z8L182 has three 8-bit bi-directional Ports. Each bit is individually programmable for input or output. The Ports consist of two registers the Port Direction Control Register and the Port Data Register. The Port and direction register can be accessed in any page of I/O space since only the lowest eight address lines are decoded ...
Page 77
... Z180 MPU is disabled and the internal /DREQ0 is equal to the complement of the Data Ready Shadow bit. If bit and bit the external /DREQ1 pin of the Z180 MPU is disabled and the internal /DREQ1 is equal to the complement or the Data Ready Shadow bit. Z80182/Z8L182 ILOG ...
Page 78
... Table 20. EV2 and EV1, Emulation Mode Control Mode 0 Mode 1 Mode 2 Mode 3 Mode 0 Normal Mode This is the normal operating mode for the Z80182/Z8L182. Mode 1 Emulation Adapter Mode The Emulation Adaptor Mode enables system development for the Z182 with a readily available Z180 emulator. The Emulator provides the Z180 ™ ...
Page 79
... Output TxA1 Output /INT0 Input SLEEP, HALT EFFECT ON MIMIC AND 182 SIGNALS The following Z80182/Z8L182 signals are driven High when Z180 ™ MPU enters a SLEEP or HALT state: /MRD when selected in the Interrupt Edge/Pin MUX Register. /MWR when selected in the Interrupt Edge/Pin MUX Register ...
Page 80
... All voltages are referenced to GND (0V). Positive current flows into the referenced pin (Figure 89). Available operating temperature range is +70 C Voltage Supply Range: +4.50V V + 5.50V Z80182 CC +3. 3.60V Z8L182 CC All AC parameters assume a load capacitance of 100 pF. Add 10 ns delay for each 50 pF increase in load maximum of 150 pF for the data bus and 100 pF for address and control lines ...
Page 81
... CC V –0.6 CC 0.40 0.40 1.0 1.0 60 120 100 200 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 50 12 Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL Unit Condition –200 –200 –200 2 2.2 mA ...
Page 82
... Min Typ Max V –0 2.0 V +0.3 CC –0.3 0.6 –0.3 0.8 2.15 V –0.6 CC 0.40 0. TBD TBD TBD TBD 4 8 TBD TBD 50 12 Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL Unit Condition –200 –200 –0 0 – ...
Page 83
... Figure 90. CPU Timing I/O Read/Write Cycle ILOG NTELLIGENT I/O Write Cycle † I/O Read Cycle † and 26a Z80182/Z8L182 P ERIPHERAL 3-83 ...
Page 84
... Acknowledge Cycle, Refresh Cycle, BUS RELEASE Mode HALT Mode, SLEEP Mode, SYSTEM STOP Mode) 3- [3] [3] Output buffer is off at this point [4] Refer to T able C, parameter 7 Figure 91. CPU Timing Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL DS971820600 ...
Page 85
... Figure 92. CPU Timing CPU or DMA Read/Write Cycle (Only DMA Write Cycle for /TENDi [ [3] 17 Figure 93. DMA Control Signals Z I ILOG NTELLIGENT I/O Write Cycle [ Z80182/Z8L182 P ERIPHERAL 29 25 [4] 3-85 ...
Page 86
... TIMING DIAGRAMS (Continued) T1 Ø D7-D0 Ø BUS RELEASE Mode E SLEEP Mode SYSTEM STOP Mode 3- Figure 94. E Clock Timing (Memory Read/Write Cycle I/O Read/Write Cycle) 49 Figure 95. E Clock Timing Z80182/Z8L182 Z I ILOG NTELLIGENT DS971820600 P ERIPHERAL ...
Page 87
... Opcode Fetch) E (I/O Write) Ø A18/TOUT DS971820600 Figure 96. E Clock Timing (Minimum timing example of PWEL and PWEH) Timer Data Reg = 0000H 55 Figure 97. Timer Output Timing Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL 3-87 ...
Page 88
... Zilog TIMING DIAGRAMS (Continued) SLP Instruction Fetch T3 T1 Ø /INTi /NMI A18-A0 /MREQ, /M1 /RD /HALT 3- Figure 98. SLEEP Execution Cycle Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL Next Opcode Fetch DS971820600 ...
Page 89
... DS971820600 tcyc 58 59 11.5 tcyc 16.5 tcyc 60 61 Figure 99. CSI/O Receive/Transmit Timing Figure 100 /ROMCS and /RAMCS Timing Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL tcyc 58 59 11.5 tcyc 16.5 tcyc 60 61 3-89 ...
Page 90
... Figure 102. External Clock Rise Time and Fall Time 3- Address Valid Figure 101. /MWR and /MRD Timing 66 70 VIL1 Figure 103. Input Rise and Fall Time Z80182/Z8L182 Z I ILOG NTELLIGENT (Except EXTAL, /RESET) ...
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... Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL Z8S180 33 MHz Min Max Unit Note 30 2000 ...
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... MHz Min Max 7.5 tcyc+100 Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL Z8S180 33 MHz Min Max Unit Note ...
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... Rise to /DTR//REQ Not Valid Delay 6 TdPC(INT) Clock to /INT Valid Delay DS971820600 Figure 104. ESCC AC Parameter Table B. ESCC Timing Parameters Min Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL 5 20 MHz Max Unit ...
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... External /TRxC, /RTxC Transmit TxD 13 /TRxC Output /RTxC /TRxC /CTS, /DCD /SYNC Input 3- Figure 105. General Timing Diagram Z80182/Z8L182 Z I ILOG NTELLIGENT DS971820600 P ERIPHERAL ...
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... RTxC High Width TRxC Low Width RTxC Cycle Time DPLL Cycle Time Min Crystal Osc. Period TRxC High Width TRxC Low Width TRxC Cycle Time DCD or CTS Pulse Width SYNC Pulse Width Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL 20 MHz Min Max Notes ...
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... Wait /SYNC Output /INT /RTxC, /TRxC Transmit /W//REQ Request /W//REQ Wait /DTR//REQ Request /INT /CTS, /DCD /SYNC Input /INT 3- Figure 106. Z85230 System Timing Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL DS971820600 ...
Page 97
... Z8L182 Z80182 20 MHz 33 MHz Min Max Min Max Z8L182 Z80182 20 MHz 33 MHz Min Max Min Max 3-97 ...
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... T2 TW Port Data Reg. Addr. (Input Port Output Data 2 (In Port Output Data 1 (Out) Port Output Data 2 (Out) Port Data Reg. F5 Port Data 1 (Out) Port Data 2 Out Port Input Data 2 (In) DS971820600 Z80182/Z8L182 P ERIPHERAL ...
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... Zilog Read Write External Bus Master Timing Address A7-A0 /IORQ /RD Data /WR Data Figure 108. Read/Write External Bus Master Timing DS971820600 Data In Z80182/Z8L182 Z I ILOG NTELLIGENT F5 F7 Data Out ERIPHERAL 3-99 ...
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... These AC parameter values are preliminary and are subject to change without notice. [1] Applies only between transactions involving the ESCC ESCC clock period time CC 3-100 Z8L182 20 MHz Min Max 4TcC 4TcC Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL Z80182 33 MHz Min Max Units Notes 4TcC ns [1] 4TcC ns DS971820600 ...
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... Valid Figure 110. PC Host /RD /WR Timing Table H. PC Host /RD /WR Timing Z8L182 20 MHz Min Z80182/Z8L182 ILOG NTELLIGENT Z80182 33 MHz Max Min Max Units ERIPHERAL 3-101 ...
Page 102
... These AC parameter values are preliminary and are subject to change without notice. 3-102 Valid Valid Z8L182 20 MHz Min Max 30 30 2.5 MPU Clock Cycles 125 100 125 Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL Z80182 33 MHz Min Max Units 2.5 MPU ns Clock Cycles 125 ns 100 ns 125 ns DS971820600 ...
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... DS971820600 /HRD /HDDIS 13 Figure 113. Driver Enable Timing Table J. Driver Enable Timing Z8L182 20 MHz Min Max Figure 114. Interrupt Timing RCVR FIFO Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL Z80182 33 MHz Min Max Units 3-103 ...
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... Figure 115. Interrupt Timing Transmitter FIFO 3-104 Table K. Interrupt Timing RCVR FIFO Z8L182 20 MHz Min 2 MPU Clock Cycles 2 MPU Clock Cycles 16 Z80182/Z8L182 Z I ILOG NTELLIGENT Z80182 33 MHz Max Min Max 2 MPU Clock Cycles 2 MPU Clock Cycles 17 18 DS971820600 P ERIPHERAL ...
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... Figure 116 RCVR FIFO Bytes Other Than First DS971820600 Table L. Interrupt Timing Transmitter FIFO Z8L182 20 MHz Min Clock Cycles 2 MPU Clock Cycles Z80182/Z8L182 Z I ILOG NTELLIGENT Z80182 33 MHz Max Min Max 2.5 MPU 2.5 MPU Clock Cycles 2 MPU Clock Cycles ERIPHERAL 3-105 ...
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... Delay From Start to /HTxRDY Active Note: These AC parameter values are preliminary and are subject to change without notice. Clock Generator The Z80182/Z8L182 ZIP ™ uses the Z182 MPUs on-chip clock generator to supply system clock. The required clock is easily generated by connection a crystal to the external terminals (XTAL,EXTAL) ...
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... Zilog PACKAGE INFORMATION DS971820600 100-Pin VQFP Package Diagram Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL 3-107 ...
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... Zilog PACKAGE INFORMATION (Continued) 3-108 100-Pin QFP Package Diagram Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL DS971820600 ...
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... MHZ Environmental C = Plastic Standard D = Plastic Stressed E = Hermetric Standard Example: Z 80182 Z80182, 20 MHz, QFP +70 C, Plastic Standard Flow Environmental Flow T emperature Package Speed Product Number Zilog Prefix © 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc ...