Z80182 Zilog., Z80182 Datasheet - Page 59

• Manufacturer Part Number: Z80182
• Description: Z8018x Family MPU
• Manufacturer: Zilog.

Z182 MISCELLANEOUS CONTROL AND INTERFACE REGISTERS
/RAMCS AND /ROMCS REGISTERS
To assist decoding of ROM and RAM blocks of memory,
three more registers and two pins have been added to the
DS971820600
Bit 3 Disable ROMs
If this bit is 1, it disables the ROMCS pin. If it is 0, addresses
below the ROM boundary set by the ROMBR register will
cause the ROMCS pin to go Low.
Bit 2 Tri-Muxed Pins Select
The Z80182/Z8L182 has three pins that are triple
multiplexed and controlled by bit 2 and bit 1. Table 14
shows the different modes.
Zilog
Table 14. SCR Control for Triple Multiplexed Pins
Upon reset
Bit 2
0
0
1
1
(Z180 MPU Read/Write, Address xxE6H)
D7 D6 D5 D4 D3 D2 D1 D0
1
Bit 1
0
1
0
1
1
Figure 55. RAMUBR
1
System Configuration Register
/TEND1,TxS,CKS
/TEND1,TxS,CKS
/RTSB,(/DTR//REQB),(/W//REQB)
/HRxRDY,//HTxRDY,HINTR
1
1
1
1
1
P R E L I M I N A R Y
A19-A12
Bit 1 ESCC
If this bit is 0, Mode 0 is selected.
If this bit is 1, Mode 1 is selected.
Mode 0:
Channel A ESCC Enabled
Channel B ESCC Enabled
PIA Port Enabled
16550 MIMIC Interface Disabled
Mode 1:
Channel A ESCC enabled
Channel B outputs disabled
PIA disabled
16550 MIMIC Interface Enabled
Bit 0 Daisy Chain
This bit is used to set interrupt priority of the ESCC and
16550 MIMIC interface. If it is 0, the ESCC is higher up in
the daisy chain than the 16550 MIMIC interface. If it is 1, the
16550 interface is higher up than the ESCC. Note that
/INT0 is used for both MIMIC and ESCC Interrupts.
Z80182/Z8L182. The two pins are /ROMCS and /RAMCS.
The three registers are RAMUBR, RAMLBR and ROMBR.
Upon reset
(Z180 MPU Read/Write, Address xxE7H)
™
D7 D6 D5 D4 D3 D2 D1 D0
1
Channel B/MIMIC
1
Figure 56. RAMLBR
1
1
1
1
Z
1
ILOG
1
I
NTELLIGENT
A19-A12
Z80182/Z8L182
P
ERIPHERAL
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