Z80182 Zilog., Z80182 Datasheet - Page 95

• Manufacturer Part Number: Z80182
• Description: Z8018x Family MPU
• Manufacturer: Zilog.

Notes:
These AC parameter values are preliminary and subject to change without notice.
[1] RxC is /RTxC or /TRxC, whichever is supplying the receive clock.
[2] TxC is /TRxC or /RTxC, whichever is supplying the transmit clock.
[3] Both /RTxC and /SYNC have 30 pF capacitors to ground connected to them.
[4] Synchronization of RxC to PCLK is eliminated in divide by four operation.
[5] Parameter applies only to FM encoding/decoding.
[6] Parameter applies only for transmitter and receiver; DPLL and baud
[7] The maximum receive or transmit data rate is 1/4 PCLK.
[8] Applies to DPLL clock source only. Maximum data rate of 1/4 PCLK
DS971820600
Zilog
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16a
16b
17
18
19
20
21
22
still applies. DPLL clock should have a 50% duty cycle.
rate generator timing requirements are identical to case PCLK requirements.
Symbol
TdPC(REQ)
TdPC(W)
TsRxC(PC)
TsRxD(RxCr)
ThRxD(RxCr)
TsRxD(RxCf)
ThRxD(RxCf)
TsSY(RxC)
ThSY(RXC)
TsTxC(PC)
TdTxCf(TXD)
TdTxCr(TXD)
TdTxD(TRX)
TwRTxh
TwRTxI
TcRTx
TxRx(DPLL)
TcRTxx
TwTRxh
TwTRxl
TcTRx
TwExT
TwSY
Table C. Z85230 General Timing Table
Parameter
/PCLK to Wait Inactive
/RxC to /PCLK Setup Time
RxD to /RxC Hold Time
RxD to /RxC Hold Time
/SYNC to/RxC Hold Time
RTxC Cycle Time
DPLL Cycle Time Min
/PCLK to W/REQ Valid
RxD to /RxC Setup Time
RxD to /RxC Setup Time
/SYNC to /RxC Setup Time
/TxC to /PCLK Setup Time
/TxC to TxD Delay
/TxC to TxD Delay
TxD to TRxC Delay
RTxC High Width
TRxC Low Width
Crystal Osc. Period
TRxC High Width
TRxC Low Width
TRxC Cycle Time
DCD or CTS Pulse Width
SYNC Pulse Width
P R E L I M I N A R Y
5TcPc
Min
N/A
–90
N/A
200
200
45
45
70
70
50
61
70
70
60
60
0
20 MHz
1000
Max
170
70
70
70
70
0
Z
ILOG
I
NTELLIGENT
Z80182/Z8L182
Notes
[1,4]
[1,5]
[1,5]
[2,4]
[2,5]
[6,7]
[7,8]
[6,7]
[1]
[1]
[1]
[1]
[2]
[6]
[6]
[3]
[6]
[6]
P
ERIPHERAL
3-95