Z80182 Zilog., Z80182 Datasheet - Page 79

• Manufacturer Part Number: Z80182
• Description: Z8018x Family MPU
• Manufacturer: Zilog.

SLEEP, HALT EFFECT ON MIMIC AND 182 SIGNALS
The following Z80182/Z8L182 signals are driven High
when Z180
DS971820600
EMULATION MODES (Continued)
Signal
PHI
/M1
/MREQ,/MRD
/IORQ
/RD
/WR
/RFSH
/HALT
ST
E
/BUSACK
/WAIT
A19,A18/T
A17-A0
D7-D0
TxA0
/RTS0
TxA1
/INT0
Zilog
/MRD when selected in the Interrupt
Edge/Pin MUX Register.
/MWR when selected in the Interrupt
Edge/Pin MUX Register.
/ROMCS,/RAMCS always High in
SLEEP or HALT.
OUT
™
MPU enters a SLEEP or HALT state:
Table 21. Emulation Mode 1
Input/Output
Normal
Mode 0
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Emulation Adaptor
Output, Open-Drain
Input/Output
Tri-state
Tri-state
Tri-state
Tri-state
Mode 1
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
P R E L I M I N A R Y
Mode 2 Emulation Probe Mode
In the Emulator Probe Mode all of the Z182 output signals
are tri-state. This scheme allows a Z182 emulator probe to
grab on to the Z182 package leads on the target system.
Mode 3 RESERVED (for test purposes only)
This mode is reserved for test purpose only, do not use.
Notes:
Z182 has two branches of reset. /RESET controls the Z182
overall configuration, RAM and ROM boundaries, plus the
ESCC, Port and the 16550 MIMIC interface. In Normal
Mode, a "one shot" circuit samples the input of the /RESET
pin to assert the internal reset to its proper duration. In
Adapter Mode, this "one shot" circuit is bypassed. Note
also that the Z180’s crystal oscillator is disabled in Mode
1 and Mode 2.
In Mode 1 the emulator must provide /MREQ on the
(/MREQ,/MRD) Z80182/Z8L182 pin (not /MRD); and A18
(not T
The following signals are High-Z during SLEEP and HALT:
A0-A19 (A18 if selected) always High-Z in power down.
D0-D7 always High-Z in power down modes.
The MIMIC logic of the 182 is disabled during power down
modes of the Z180.
OUT
/IOCS when so selected in the Interrupt
Edge/Pin MUX Register.
/RD and /WR.
) on the A18/T
OUT
pin.
Z
ILOG
I
NTELLIGENT
Z80182/Z8L182
P
ERIPHERAL
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