Z80182 Zilog., Z80182 Datasheet - Page 21

• Manufacturer Part Number: Z80182
• Description: Z8018x Family MPU
• Manufacturer: Zilog.

16550 MIMIC INTERFACE FUNCTIONAL DESCRIPTION
The Z80182/Z8L182 has a 16550 MIMIC interface that
allows it to mimic the 16550 device. It has all the interface
pins necessary to connect to the PC/XT/AT bus. It contains
the complete register set of the part with the same interrupt
structure. The data path allows parallel transfer of data to
and from the register set by the internal Z80180 of the
Z80182/Z8L182. There is no shift register associated with
the mimic of the 16550 UART. This interface saves the
application from doing a serial transfer before performing
data compression or error correction on the data.
Control of the register set is maintained by six priority
encoded interrupts to the Z80182/Z8L182. When the PC/
XT/AT writes to THR, MCR, LCR, DLL, DLM, FCR or reads
the RBR, an interrupt to the Z80182/Z8L182 is generated.
Each interrupt can be individually masked off or all interrupts
can be disabled by writing a single bit. Both mode 0 and
mode 2 interrupts are supported by the 16550 MIMIC
interface.
DS971820600
Zilog
PC DMA CNTL
PC IRQ
PC
Addr/Decode
PC
Databus
or PC Side Interface
16550 MIMIC Side
1
4
8
2
16550 MIMIC
Register Set
Figure 6. 16550 MIMIC Block Diagram
PC IRQ
P R E L I M I N A R Y
6
Two eight-bit timers are also available to control the data
transfer rate of the 16550 MIMIC interface. Their input is
tied to the ESCC channel B divide clock, so a down count
of 24 bits is possible. An additional two eight bit timers are
available for programming the FIFO timeout feature (Four
Character Time Emulation) for both Receive and Transmit
FIFO’s.
The 16550 MIMIC interface supports the PC/XT/AT interrupt
structure as well as an additional mode that allows for a
wired Logic AND interrupt structure.
The 16550 MIMIC interface is also capable of high speed
parallel DMA transfers by using two control lines and the
transmit and receive registers of the 16550 MIMIC interface.
All registers of the 16550 MIMIC interface are accessible
in any page of I/O space since only the lowest eight
address lines are decoded. See Figure 6 for a block
diagram of the 16550 MIMIC interface.
Databus
Transmit
Receive
Z80180
Control
Timer
Timer
Control
IRQ
DMA
Register
Control/
Z
Config
ILOG
Databus
Z80180
I
Z80180
NTELLIGENT
Control
DMA
8
2
MPU Side
Z80182/Z8L182
Interface
Z80180
Address
P
ERIPHERAL
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