VSC8117QP2 VITESSE [Vitesse Semiconductor Corporation], VSC8117QP2 Datasheet - Page 10

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VSC8117QP2

Manufacturer Part Number
VSC8117QP2
Description
ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery
Manufacturer
VITESSE [Vitesse Semiconductor Corporation]
Datasheet
ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery
Page 10
Table 4: Transmit Data Input Timing Table (STS-12 Operation)
Table 5: Transmit Data Input Timing Table (STS-3 Operation)
Note: Duty cycle for TXLSCKOUT is 50% +/- 10% worst case
Table 6: Receive Data Output Timing Table (STS-12 Operation)
Parameter
Parameter
Parameter
T
T
T
T
T
RXCLKIN
RXVALID
CLKOUT
RXLSCK
T
CLKOUT
T
T
T
T
INSU
INSU
INH
INH
PW
RXLSCKOUT
RXOUT [7:0]
RXCLKIN+
RXCLKIN-
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
FP
Transmit data output byte clock period
Transmit data setup time with respect to TXLSCKOUT
Transmit data hold time with respect to TXLSCKOUT
Receive clock period
Receive data output byte clock period
Time data on RXOUT [7:0] and FP is valid before and
after the rising edge of RXLSCKOUT
Pulse width of frame detection pulse FP
Transmit data output byte clock period
Transmit data setup time with respect to TXLSCKOUT
Transmit data hold time with respect to TXLSCKOUT
Figure 10: Receive Data Output Timing Diagram
A1
VITESSE
VITESSE SEMICONDUCTOR CORPORATION
SEMICONDUCTOR CORPORATION
T
Description
Description
Description
RXCLKIN
T
RXLSCK
A2
T
RXVALID
A2
Min
Min
Min
1.0
1.0
1.0
1.0
4.0
-
-
-
-
-
A2
51.44
12.86
12.86
1.608
12.86
Typ
Typ
Typ
-
-
-
-
-
T
A2
RXVALID
Max
Max
Max
-
-
-
-
-
-
-
-
-
-
VSC8117
Data Sheet
G52221-0, Rev 4.1
Units
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1/8/00

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