VSC8117QP2 VITESSE [Vitesse Semiconductor Corporation], VSC8117QP2 Datasheet - Page 20

• Manufacturer Part Number: VSC8117QP2
• Description: ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery
• Manufacturer: VITESSE [Vitesse Semiconductor Corporation]

ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery
Page 20
Application Notes
DC Coupling and Terminating High-speed PECL I/Os
use 3.3/5V programmable PECL I/Os which can be direct coupled to either +3.3V PECL or +5V PECL signals
from the optics. These PECL levels are essentially ECL levels shifted positive by 3.3 volts or 5 volts. These
PECL I/Os are referenced to the V
either 3.3V or 5V interface, the V
ingly.
AC Coupling and Terminating High-speed PECL I/Os
VSC8117 as well. The PECL receiver inputs of the VSC8117 are internally biased at VDD/2. Therefore, AC-
coupling to the VSC8117 inputs is accomplished by providing the pull-down resistor for the open-source PECL
output and an AC-coupling capacitor used to eliminate the DC component of the output signal. This capacitor
allows the PECL receivers of the VSC8117 to self-bias via its internal resistor divider network (see Figure 13).
level, a pull-down resistor, traditionally connected to VDD-2.0V, is needed when the output FET is turned off.
Since VDD-2.0V is usually not present in the system, the resistor could be terminated to ground for conve-
nience. The VSC8117 output drivers should be either AC-coupled to the 5.0V PECL inputs of the optics mod-
ule, or translated (DC level shift). Appropriate biasing techniques for setting the DC-level of these inputs should
be employed.
equivalent circuit as shown in Figure 12. The figure shows the appropriate termination values when interfacing
3.3V PECL to 5.0V PECL. This network provides the equivalent 50 ohm termination for the high speed I/Os
and also provides the required dc biasing for the receivers of the optics module. Table 17 contains recommended
values for each of the components.
TTL Input Structure
erances (see Table 13). The input structure, shown in Figure 13, uses a current limiter to avoid overdriving the
input FETs.
Layout of the High Speed Signals
include using controlled impedance lines and keeping the distance between components to an absolute mini-
mum. PECL signals need 50-ohm traces, and TTL signals need 75-ohm traces. In addition, stubs should be kept
at a minimum as well as any routing discontinuities. This will help minimize reflections and ringing on the high
speed lines and insure the maximum eye opening. In addition the output pull down resistor should be placed as
close to the VSC8117 pin as possible while the AC-coupling capacitor and the biasing resistors should be
placed as close as possible to the optics input pin. The same is true on the receive circuit side. Using small out-
line components and minimum pad sizes also helps in reducing discontinuities.
The high speed signals on the VSC8117 (RXDATAIN, RXCLKIN, TXDATAOUT, REFCLKP, LOSPECL)
If the optics modules provide ECL level interface, the high speed signals can be AC coupled to the
The PECL output drivers are capable of sourcing current but not sinking it. To establish a LOW output
The dc biasing and 50 ohm termination requirements can easily be integrated together using a thevenin
The TTL inputs of the VSC8117 are 3.3V TTL which can accept 5.0V TTL levels within a given set of tol-
The routing of the High Speed signals should be done using good high speed design practices. This would
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pin (pins 4 and 10) is required to connect to 3.3V or 5V supplies accord-
supply (VDDP) and are terminated to ground. To program these I/Os for
VSC8117
Data Sheet
G52221-0, Rev 4.1
1/8/00