VSC8117QP2 VITESSE [Vitesse Semiconductor Corporation], VSC8117QP2 Datasheet - Page 12

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VSC8117QP2

Manufacturer Part Number
VSC8117QP2
Description
ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery
Manufacturer
VITESSE [Vitesse Semiconductor Corporation]
Datasheet
ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery
Page 12
Table 11: Clock Multiplier Unit Performance
(1)
(2)
Note: Jitter specification is defined utilizing a 12KHz - 5MHz LP-HP single pole filter.
AC Characteristics
Table 12: PECL and TTL Outputs
DC Characteristics
Table 13: PECL and TTL Inputs and Outputs
Parameters
Parameters
T
T
V
V
T
Name
T
V
V
R,PECL
RCd
F,PECL
OUT75
RCj
RCj
RC
These Reference Clock Jitter limits are required for the outputs to meet SONET system level jitter requirements
(< 10 mUIrms)
Needed to meet SONET output frequency stability requirements
OCM
R,TTL
F,TTL
OH
OL
f
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Output HIGH
voltage (PECL)
Output LOW
voltage (PECL)
O/P Common
Mode Range
(PECL)
Differential
Output Voltage
(PECL)
Reference clock duty cycle
Reference clock jitter (RMS) @ 77.76 MHz ref
Reference clock jitter (RMS) @ 19.44 MHz ref
Reference clock frequency tolerance
TTL Output Rise Time
TTL Output Fall Time
PECL Output Rise Time
PECL Output Fall Time
Description
Description
VITESSE
VITESSE SEMICONDUCTOR CORPORATION
SEMICONDUCTOR CORPORATION
Description
Min
600
0.7
1.1
(2)
Typ
Min
(1)
(1)
V
V
Typ
350
350
DDP
DDP
1.5
2
Max
1300
– 0.9V
– 1.3V
Min
-20
40
Max
Units
Units
Typ
ns
ns
ps
ps
mV
V
V
V
10-90%
10-90%
20-80%
20-80%
75 to V
Max
+20
60
13
5
Conditions
Conditions
VSC8117
Data Sheet
G52221-0, Rev 4.1
DDP
Units
– 2.0 V
ppm
%
ps
ps
1/8/00

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