VSC8117QP2 VITESSE [Vitesse Semiconductor Corporation], VSC8117QP2 Datasheet - Page 6

• Manufacturer Part Number: VSC8117QP2
• Description: ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery
• Manufacturer: VITESSE [Vitesse Semiconductor Corporation]

ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery
Page 6
Split Loopback
received (RXDATAIN) is mux’d through to the high-speed serial output (TXDATAOUT). The low-speed trans-
mit byte wide bus(TXIN[7:0]) and (TXLSCKIN) are mux’d into the low-speed byte wide receive output bus
(RXOUT[7:0]) and (RXLSCKOUT). See Figure 5.
Loop Timing
is bypassed by using the receive clock (RXCLKIN), and the entire part is synchronously clocked from a single
external source.
Clock Synthesis
clock used for serialization in the transmitter section. The PLL is comprised of a phase-frequency detector
(PFD), an integrating operation amplifier and a voltage controlled oscillator (VCO) configured in classic feed-
back system. The PFD compares the selected divided down version of the 622MHz VCO (pin CMUFREQSEL
selects the divide-by ratios of 8 or 32, see Table 10) and the reference clock. The integrator provides a transfer
function between input phase error and output voltage control. The VCO portion of the PLL is a voltage con-
trolled ring-oscillator with a center frequency of 622MHz.
amplifier through the CP1, CP2, CN1 and CN2 pins. The configuration of these external surface mounted
capacitors is shown in Figure 6. Table 1 shows the recommended external capacitor values for the configurable
reference frequencies.
Equipment and facility loopback modes can be enabled simultaneously. In this case, high-speed serial data
LOOPTIM0 mode bypasses the CMU when the LOOPTIM0 input is asserted high. In this mode the CMU
The VSC8117 uses an integrated phase-locked loop (PLL) for clock synthesis of the 622MHz high speed
The reactive elements of the integrator are located off-chip and are connected to the feedback loop of the
TXDATAOUT
RXDATAIN
DSBLCRU
RXCLKIN
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]
Recovered
Clock
CRU
VITESSE
VITESSE SEMICONDUCTOR CORPORATION
SEMICONDUCTOR CORPORATION
0
1
Figure 5: Split Loopback Datapath
D
Q D
Q
PLL
Serial to
Parallel
Parallel to
Serial
1:8
8:1
8
Q D
D
Q
TXLSCKIN
RXOUT[7:0]
RXLSCKOUT
TXIN[7:0]
VSC8117
Data Sheet
G52221-0, Rev 4.1
1/8/00