EP1AGX ALTERA [Altera Corporation], EP1AGX Datasheet - Page 101

• Manufacturer Part Number: EP1AGX
• Description: Section I. Arria GX Device Data Sheet
• Manufacturer: ALTERA [Altera Corporation]

Chapter 2: Arria GX Architecture
I/O Structure
Figure 2–78. Arria GX I/O Banks
Notes to
(1)
(2) Depending on the size of the device, different device members have different numbers of V
(3) Banks 9 through 12 are enhanced PLL external clock output banks.
(4) Horizontal I/O banks feature SERDES and DPA circuitry for high-speed differential I/O standards. For more information about differential I/O
On-Chip Termination
© December 2009 Altera Corporation
Figure 2–78
and the Quartus II software.
standards, refer to the
Figure
PLL8
PLL7
PLL1
PLL2
2–78:
VREF0B3 VREF1B3 VREF2B3 VREF3B3 VREF4B3
VREF4B8 VREF3B8 VREF2B8 VREF1B8 VREF0B8
is a top view of the silicon die that corresponds to a reverse view for flip chip packages. It is a graphical representation only.
This I/O bank supports LVDS
and LVPECL standards for input clock operation.
Differential HSTL and differential
SSTL standards are supported
for both input and output operations. (3)
DQS ×8
This I/O bank supports LVDS
and LVPECL standards
for input clock operations. Differential HSTL
and differential SSTL standards
are supported for both input
and output operations. (3)
DQS ×8
High-Speed Differential I/O Interfaces in Arria GX Devices
Each I/O bank has its own VCCIO pins. A single device can support
1.5-, 1.8-, 2.5-, and 3.3-V interfaces; each bank can support a different V
independently. Each bank also has dedicated VREF pins to support the
voltage-referenced standards (such as SSTL-2).
Each I/O bank can support multiple standards with the same V
output pins. Each bank can support one V
3.3 V, a bank can support LVTTL, LVCMOS, and 3.3-V PCI for inputs and outputs.
Arria GX devices provide differential (for the LVDS technology I/O standard) and
on-chip series termination to reduce reflections and maintain signal integrity. There is
no calibration support for these on-chip termination resistors. On-chip termination
simplifies board design by minimizing the number of external termination resistors
required. Termination can be placed inside the package, eliminating small stubs that
can still lead to reflections.
DQS ×8
DQS ×8
Bank 3
Bank 8
DQS ×8
DQS ×8
(Note
I/O banks 7, 8, 10 and 12 support all single-ended I/O
standards for both input and output operations. All differential
I/O standards are supported for both input and output operations
at I/O banks 10 and 12.
I/O Banks 3, 4, 9, and 11 support all single-ended
I/O standards for both input and output operations.
All differential I/O standards are supported for both
input and output operations at I/O banks 9 and 11.
DQS ×8
DQS ×8
I/O banks 1 & 2 support LVTTL, LVCMOS,
2.5 V, 1.8 V, 1.5 V, SSTL-2, SSTL-18 class I,
LVDS, pseudo-differential SSTL-2 and pseudo-differential
SSTL-18 class I standards for both input and output
operations. HSTL, SSTL-18 class II,
pseudo-differential HSTL and pseudo-differential
SSTL-18 class II standards are only supported for
input operations. (4)
1),
(2)
Bank 11
Bank 12
PLL11
PLL12
Bank 9
Bank 10
PLL5
PLL6
VREF0B4 VREF1B4 VREF2B4 VREF3B4 VREF4B4
VREF4B7 VREF3B7 VREF2B7 VREF1B7 VREF0B7
DQS ×8
DQS ×8
This I/O bank supports LVDS
and LVPECL standards for input clock
operation. Differential HSTL and differential
SSTL standards are supported
for both input and output operations. (3)
DQS ×8
DQS ×8
chapter.
REF
This I/O bank supports LVDS
and LVPECL standards for input clock
operation. Differential HSTL and
differential SSTL standards are
supported for both input and output
operations. (3)
voltage level. For example, when V
DQS ×8
DQS ×8
Bank 4
Bank 7
REF
groups. For the exact locations, refer to the pin list
DQS ×8
DQS ×8
DQS ×8
DQS ×8
Arria GX Device Handbook, Volume 1
CCIO
Transmitter: Bank 13
Receiver: Bank 13
REFCLK: Bank 13
Transmitter: Bank 14
Receiver: Bank 14
REFCLK: Bank 14
Transmitter: Bank 15
Receiver: Bank 15
REFCLK: Bank 15
for input and
CCIO
level
CCIO
2–95
is