EP1AGX ALTERA [Altera Corporation], EP1AGX Datasheet - Page 89

• Manufacturer Part Number: EP1AGX
• Description: Section I. Arria GX Device Data Sheet
• Manufacturer: ALTERA [Altera Corporation]

Chapter 2: Arria GX Architecture
I/O Structure
Figure 2–68. Row I/O Block Connection to the Interconnect
Note to
(1) The 32 data and control signals consist of eight data out lines: four lines each for DDR applications io_dataouta[3..0] and
© December 2009 Altera Corporation
io_dataoutb[3..0], four output enables io_oe[3..0], four input clock enables io_ce_in[3..0], four output clock enables
io_ce_out[3..0], four clocks io_clk[3..0], four asynchronous clear and preset signals io_aclr/apreset[3..0], and four
synchronous clear and preset signals io_sclr/spreset[3..0].
Figure
2–68:
Interconnect
LAB Local
Interconnects
to Adjacent LAB
R4 & R24
Interconnect
Figure 2–68
Direct Link
LAB
shows how a row I/O block connects to the logic array.
io_dataina[3..0]
io_datainb[3..0]
C4 Interconnect
to Adjacent LAB
Interconnect
Direct Link
I/O Block Local
Interconnect
io_clk[7:0]
32
Horizontal
I/O Block
up to Four IOEs
Block Contains
Horizontal I/O
Arria GX Device Handbook, Volume 1
32 Data & Control
Signals from
Logic Array (1)
2–83