EP1AGX ALTERA [Altera Corporation], EP1AGX Datasheet - Page 154

• Manufacturer Part Number: EP1AGX
• Description: Section I. Arria GX Device Data Sheet
• Manufacturer: ALTERA [Altera Corporation]

4–32
Typical Design Performance
User I/O Pin Timing
Arria GX Device Handbook, Volume 1
Table 4–47. Default Loading of Different I/O Standards for Arria GX Devices (Part 2 of 2)
The following section describes the typical design performance for the Arria GX
device family.
Table 4–48
buffer t
non-PLL global clock (GCLK) and a PLL driven global clock (GCLK-PLL). For t
and t
to the GCLK/GCLK-PLL values for the device.
EP1AGX20 I/O Timing Parameters
Table 4–48
EP1AGX20 devices for I/O standards which support general purpose I/O pins.
Table 4–48
Arria GX devices.
1.8 V
1.5 V
PCI
PCI-X
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
Differential SSTL-2 Class I
Differential SSTL-2 Class II
Differential SSTL-18 Class I
Differential SSTL-18 Class II
1.5-V differential HSTL Class I
1.5-V differential HSTL Class II
1.8-V differential HSTL Class I
1.8-V differential HSTL Class II
LVDS
CO
SU
using regional clock, add the value from the adder tables listed for each device
, t
through
through
describes the row pin delay adders when using the regional clock in
H
I/O Standard
, and t
CO
Table 4–77
Table 4–51
are reported for the cases when I/O clock is driven by a
show user I/O pin timing for Arria GX devices. I/O
show the maximum I/O timing parameters for
Capacitive Load
10
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Chapter 4: DC and Switching Characteristics
© December 2009 Altera Corporation
Typical Design Performance
Units
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
SU
, t
H
,