EP1AGX ALTERA [Altera Corporation], EP1AGX Datasheet - Page 46

• Manufacturer Part Number: EP1AGX
• Description: Section I. Arria GX Device Data Sheet
• Manufacturer: ALTERA [Altera Corporation]

2–40
Shared Arithmetic Mode
Figure 2–36. ALM in Shared Arithmetic Mode
Note to
(1) Inputs dataf0 and dataf1 are available for register packing in shared arithmetic mode.
Arria GX Device Handbook, Volume 1
Figure
2–36:
datae0
datae1
datab
dataa
datad
datac
The other half of the ALMs in the LAB is available for implementing narrower fan-in
functions in normal mode. Carry chains that use the top four ALMs in the first LAB
carries into the top half of the ALMs in the next LAB within the column. Carry chains
that use the bottom four ALMs in the first LAB carries into the bottom half of the
ALMs in the next LAB within the column. Every other column of the LABs are
top-half bypassable, while the other LAB columns are bottom-half bypassable. For
more information about carry chain interconnect, refer to
on page
In shared arithmetic mode, the ALM can implement a three-input add. In this mode,
the ALM is configured with four 4-input LUTs. Each LUT either computes the sum of
three inputs or the carry of three inputs. The output of the carry computation is fed to
the next adder (either to adder1 in the same ALM or to adder0 of the next ALM in
the LAB) using a dedicated connection called the shared arithmetic chain. This shared
arithmetic chain can significantly improve the performance of an adder tree by
reducing the number of summation stages required to implement an adder tree.
Figure 2–36
2–44.
shows the ALM in shared arithmetic mode.
4-Input
4-Input
4-Input
4-Input
LUT
LUT
LUT
LUT
shared_arith_out
shared_arith_in
carry_out
carry_in
D
D
reg0
reg1
Q
Q
“MultiTrack Interconnect”
© December 2009 Altera Corporation
To general or
To general or
To general or
To general or
local routing
local routing
local routing
local routing
Chapter 2: Arria GX Architecture
Adaptive Logic Modules