EP1AGX ALTERA [Altera Corporation], EP1AGX Datasheet - Page 83

• Manufacturer Part Number: EP1AGX
• Description: Section I. Arria GX Device Data Sheet
• Manufacturer: ALTERA [Altera Corporation]

Chapter 2: Arria GX Architecture
PLLs and Clock Networks
Figure 2–64. Global and Regional Clock Connections from Top and Bottom Clock Pins and Enhanced PLL Outputs
Note to
(1) If the design uses the feedback input, you might lose one (or two if FBIN is differential) external clock output pin.
© December 2009 Altera Corporation
Figure
2–64:
Figure 2–64
top and bottom CLK pins.
The connections to the global and regional clocks from the top clock pins and
enhanced PLL outputs are shown in
the bottom clock pins are shown in
Regional
Regional
Clocks
Clocks
Clocks
Global
RCLK27
RCLK26
RCLK25
RCLK24
RCLK10
RCLK11
RCLK8
RCLK9
shows the global and regional clocking from enhanced PLL outputs and
c0 c1 c2 c3 c4 c5
c0 c1 c2 c3 c4 c5
PLL 11
PLL 12
c0 c1 c2 c3 c4 c5
c0 c1 c2 c3 c4 c5
Table
Table
PLL 5
PLL 6
2–21.
2–20. The connections to the clocks from
RCLK31
RCLK30
RCLK29
RCLK28
G15
G14
G13
G12
G4
G5
G6
G7
RCLK12
RCLK13
RCLK14
RCLK15
Arria GX Device Handbook, Volume 1
(Note 1)
2–77