ST7FLITE29 STMICROELECTRONICS [STMicroelectronics], ST7FLITE29 Datasheet - Page 113

• Manufacturer Part Number: ST7FLITE29
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

13.9 CONTROL PIN CHARACTERISTICS
13.9.1 Asynchronous RESET Pin
T
Figure 88. Typical Application with RESET pin
Notes:
1. Data based on characterization results, not tested in production.
2. The I
(I/O ports and control pins) must not exceed I
3. The R
V
4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on
RESET pin with a duration below t
5. The reset network (the resistor and two capacitors) protects the device against parasitic resets especially in noisy en-
vironments.
6. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device
can be damaged when the ST7 generates an internal reset (LVD or watchdog).
7. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below
the V
that the current sunk on the RESET pin (by an external pull-p for example) is less than the absolute maximum value spec-
ified for I
8. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure
t
w(RSTL)out
t
t
A
Symbol
ILmax
h(RSTL)in
g(RSTL)in
Required if LVD is disabled
EXTERNAL
V
R
CIRCUIT
= -40°C to 125°C, unless otherwise specified
V
V
V
hys
ON
RESET
OL
IL
IL
IH
USER
and V
max. level specified in
IO
INJ(RESET)
ON
current sunk must always respect the absolute maximum rating specified in
5)
Recommended
pull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin between
Input low level voltage
Input high level voltage
Schmitt trigger voltage hysteresis
Output low level voltage
Pull-up equivalent resistor
Generated reset pulse duration
External reset pulse hold time
Filtered glitch duration
if LVD is disabled
DD
in
section 13.2.2 on page
V
DD
Parameter
0.01 F
0.01 F
section 13.9.1 on page
h(RSTL)in
5)
2)
V
DD
3) 1)
4.7k
4)
can be ignored.
92.
VSS
1)
.
R
ON
113. Otherwise the reset will not be taken into account internally.
V
V
V
V
Internal reset sources
DD
DD
DD
DD
6)7)8)
=5V
=5V
=3V.
Filter
Conditions
I
I
IO
IO
=+5mA T
=+2mA T
GENERATOR
T
T
A
A
A
A
PULSE
85°C
85°C
85°C
85°C
Section 13.2.2
0.7xV
Min
20
40
20
DD
Typ
0.5
0.2
200
40
70
30
2
and the sum of I
INTERNAL
RESET
0.3xV
WATCHDOG
Max
LVD RESET
ST7LITE2
120
1.0
1.2
0.4
0.5
80
ST72XXX
DD
113/131
Unit
k
ns
V
V
V
s
s
IO