ST7FLITE29 STMICROELECTRONICS [STMicroelectronics], ST7FLITE29 Datasheet - Page 72

• Manufacturer Part Number: ST7FLITE29
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST7LITE2
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.4.3.2 Slave Select Management
As an alternative to using the SS pin to control the
Slave Select signal, the application can choose to
manage the Slave Select signal by software. This
is configured by the SSM bit in the SPICSR regis-
ter (see
free for other application uses and the internal SS
signal level is driven by writing to the SSI bit in the
SPICSR register.
In Master mode:
Figure 44. Generic SS Timing Diagram
Figure 45. Hardware/Software Slave Select Management
72/131
1
In software management, the external SS pin is
– SS internal must be held high continuously
MOSI/MISO
(if CPHA=0)
(if CPHA=1)
Figure
Master SS
Slave SS
Slave SS
45)
SS external pin
SSI bit
Byte 1
SSM bit
1
0
In Slave Mode:
There are two cases depending on the data/clock
timing relationship (see
If CPHA=1 (data latched on 2nd clock edge):
If CPHA=0 (data latched on 1st clock edge):
SS internal
Byte 2
– SS internal must be held low during the entire
– SS internal must be held low during byte
transmission. This implies that in single slave
applications the SS pin either can be tied to
V
ing the SS function by software (SSM= 1 and
SSI=0 in the in the SPICSR register)
transmission and pulled high between each
byte to allow the slave to write to the shift reg-
ister. If SS is not pulled high, a Write Collision
error will occur when the slave writes to the
shift register (see
SS
, or made free for standard I/O by manag-
Byte 3
Section
Figure
11.4.5.3).
44):