ST7FLITE29 STMICROELECTRONICS [STMicroelectronics], ST7FLITE29 Datasheet - Page 99

• Manufacturer Part Number: ST7FLITE29
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

13.4 SUPPLY CURRENT CHARACTERISTICS
The following current consumption specified for
the ST7 functional operating modes over tempera-
ture range does not take into account the clock
source current consumption. To get the total de-
13.4.1 Supply Current
T
Notes:
1. CPU running with memory access, all I/O pins in input mode with a static value at V
in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
2. All I/O pins in input mode with a static value at V
driven by external square wave, LVD disabled.
3. SLOW mode selected with f
V
4. SLOW-WAIT mode selected with f
V
5. All I/O pins in input mode with a static value at V
max.
6. This consumption refers to the Halt period only and not the associated run period which is software dependent.
Figure 60. Typical I
Symbol
A
SS
DD
I
DD
= -40 to +125°C unless otherwise specified
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
(no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
or V
SS
2
Supply current in RUN mode
Supply current in WAIT mode
Supply current in SLOW mode
Supply current in SLOW WAIT mode
Supply current in HALT mode
Supply current in AWUFH mode
(no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
2.5
8 MHz
4 MHz
1 MHz
3
DD
Parameter
3.5
in RUN vs. f
Vdd (V)
4
CPU
based on f
4.5
CPU
5
CPU
based on f
5)6)
5.5
OSC
divided by 32. All I/O pins in input mode with a static value at V
DD
DD
6
OSC
or V
or V
divided by 32. All I/O pins in input mode with a static value at
f
f
f
f
-40°C T
T
T
SS
CPU
CPU
CPU
CPU
SS
A
A
(no load), all peripherals in reset state; clock input (CLKIN)
(no load). Data tested in production at V
vice consumption, the two current values must be
added (except for HALT mode for which the clock
is stopped).
Figure 61. Typical I
=8MHz
=8MHz
=500kHz
=500kHz
+125°C
+25°C
Conditions
A
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
+85°C
1)
2)
3)
4)
2
2.5
250 KHz
125 KHz
62.5 Khz
3
DD
DD
3.5
or V
in SLOW vs. f
Vdd (V)
SS
4
7.5
3.7
1.6
1.6
1
15
20
Typ
(no load), all peripherals
4.5
DD
12
6
2.5
2.5
10
50
30
5
Max
max. and f
CPU
ST7LITE2
5.5
99/131
Unit
mA
DD
6
A
CPU
or
1