ISPPAC-CLK5610V-01T100C LATTICE [Lattice Semiconductor], ISPPAC-CLK5610V-01T100C Datasheet - Page 14

• Manufacturer Part Number: ISPPAC-CLK5610V-01T100C
• Description: In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Typical Performance Characteristics
Detailed Description
PLL Subsystem
The ispClock5600 provides an integral phase-locked-loop (PLL) which may be used to generate output clock sig-
nals at lower, higher, or the same frequency as a user-supplied input reference signal. The core functions of the
PLL are an edge-sensitive phase detector, a programmable loop filter, and a high-speed voltage-controlled oscilla-
tor (VCO). Additionally, a set of programmable input, output and feedback dividers (M, N, V[1..5]) is provided to
support the synthesis of different output frequencies.
Phase/Frequency Detector
The ispClock5600 provides an edge-sensitive phase/frequency detector (PFD), which means that the device will
function properly over a wide range of input clock reference duty cycles. It is only necessary that the input refer-
ence clock meet specified minimum HIGH and LOW times (t
the PFD. The PFD’s output is of a classical charge-pump type, outputting charge packets which are then integrated
by the PLL‘s loop filter.
A lock-detection feature is also associated with the PFD. When the ispClock5600 is in a LOCKED state, the LOCK
output pin goes LOW. The lock detector has two operating modes; phase lock mode and frequency lock mode. In
phase-lock mode, the LOCK signal is asserted if the phases of the reference and feedback signals match, whereas
in frequency-lock mode the LOCK signal is asserted when the frequencies of the feedback and reference signals
-100
100
-50
-75
-25
75
50
25
1.2
0.8
0.6
0.4
0.2
0
1
0
300
0
(Skew Mode = FINE, f
Typical Skew Error vs. Setting
3
400
(Normalized to 640MHz)
I
Skew Setting #
CCD
6
f
VCO
vs. f
500
(MHz)
VCO
VCO
9
= 600MHz)
600
12
700
15
14
CLOCKHI,
1.2
0.8
0.6
0.4
0.2
1
0
0
(LVCMOS 3.3V, Normalized to 320MHz)
t
5 0
CLOCKLO
ispClock5600 Family Data Sheet
I
CCO
100
Output Frequency (MHz)
) for it to be properly recognized by
vs. Output Frequency
150
200
250
300
350