ISPPAC-CLK5610V-01T100C LATTICE [Lattice Semiconductor], ISPPAC-CLK5610V-01T100C Datasheet - Page 9

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ISPPAC-CLK5610V-01T100C

Manufacturer Part Number
ISPPAC-CLK5610V-01T100C
Description
In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
Manufacturer
LATTICE [Lattice Semiconductor]
Datasheet
Lattice Semiconductor
Programmable Input and Output Termination Characteristics
R
R
OUT
IN
Symbol
Input Resistance
Output Resistance
Parameter
Rin=40Ω setting
Rin=45Ω setting
Rin=50Ω setting
Rin=55Ω setting
Rin=60Ω setting
Rin=65Ω setting
Rin=70Ω setting
Rout≈20Ω setting, VCCO=1.5V
Rout≈20Ω setting, VCCO=1.8V
Rout≈20Ω setting, VCCO=2.5V
Rout≈20Ω setting, VCCO=3.3V
Rout=40Ω setting
Rout=45Ω setting
Rout=50Ω setting
Rout=55Ω setting
Rout=60Ω setting
Rout=65Ω setting
Rout=70Ω setting
Conditions
9
ispClock5600 Family Data Sheet
Min.
40.5
49.5
36
45
54
59
61
34
38
43
47
51
55
61
Typ.
27
22
20
18
Max.
49.5
60.5
71.5
44
55
66
77
47
55
61
67
72
78
83
Units

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