ISPPAC-CLK5610V-01T100C LATTICE [Lattice Semiconductor], ISPPAC-CLK5610V-01T100C Datasheet - Page 2

• Manufacturer Part Number: ISPPAC-CLK5610V-01T100C
• Description: In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
General Description and Overview
The ispClock5610 and ispClock5620 are in-system-programmable high-fanout PLL-based clock drivers designed
for use in high performance communications and computing applications. The ispClock5610 provides up to 10 sin-
gle-ended or five differential clock outputs, while the ispClock5620 provides up to 20 single-ended or 10 differential
clock outputs. Each pair of outputs may be independently configured to support separate I/O standards (LVDS,
LVPECL, LVTTL, LVCMOS, SSTL, HSTL) and output frequency. In addition, each output provides independent pro-
grammable control of termination, slew-rate, and timing skew. All configuration information is stored on-chip in non-
volatile E
The ispClock5600’s PLL and divider systems supports the synthesis of clock frequencies differing from that of the
reference input through the provision of programmable input and feedback dividers. A set of five post-PLL V-divid-
ers provides additional flexibility by supporting the generation of five separate output frequencies. Loop feedback
may be taken internally from the output of any of the five V-dividers, or externally through FBKA+/- or FBKB+/- pins.
The core functions of all members of the ispClock5600 family are identical, the differences between devices being
restricted to the number of inputs and outputs, as shown in the following table. Figures 1 and 2 show functional
block diagrams of the ispClock5610 and ispClock5620.
Table 1. ispClock5600 Family Members
Figure 1. ispClock5610 Functional Block Diagram
FBKVTT
REFVTT
FBKA+
FBKA -
REFA+
REFA-
2
CMOS memory.
ispClock5610
ispClock5620
0
Profile Select
PS0
Device
Control
1
DIVIDER
INPUT
(1-32)
(1-32)
PS1
2
M
N
3
FEEDBACK
TDI
DIVIDER
E
2
JTAG INTERFACE
Configuration
TMS
DETECT
DETECT
PHASE
LOCK
LOCK
TCK
Ref. Input Pairs
TDO
FILTER
LOOP
1
2
RESET
VCO
2
PLL_BYPASS
Feedback Input Pairs
SKEW ADJUST
FEEDBACK
1
0
DIVIDERS
OUTPUT
1
2
(2-64)
(2-64)
(2-64)
(2-64)
(2-64)
V0
V1
V2
V3
V4
SGATE
OUTPUT ENABLE CONTROLS
ispClock5600 Family Data Sheet
OUTPUT ROUTING
GOE
MATRIX
OEX
Clock Outputs
OEY
CONTROL
SKEW
10
20
DRIVERS
OUTPUT
BANK_0A
BANK_0B
BANK_2A
BANK_2B
BANK_4A
BANK_4B
BANK_5A
BANK_5B
BANK_7A
BANK_7B