ISPPAC-CLK5610V-01T100C LATTICE [Lattice Semiconductor], ISPPAC-CLK5610V-01T100C Datasheet - Page 31

• Manufacturer Part Number: ISPPAC-CLK5610V-01T100C
• Description: In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Profile Select
The ispClock5600 stores all internal configuration data in on-board E
figuration profiles may be stored in each device. The choice of which configuration profile is to be active is specified
thought the profile select inputs PS0 and PS1, as shown in Table 7.
Table 7. Profile Select Function
Each profile controls the following internal configuration items:
The following settings are independent of the selection of active profile and will apply regardless of which profile is
selected:
If any of the above items are modified, the change will apply across all profiles. In some cases this may cause
unanticipated behavior. If multiple profiles are used in a design, the suitability of the profile independent settings
must be considered with respect to each of the individual profiles.
When a profile is changed by modifying the values of the PS0 and PS1 inputs, it may be necessary to assert a
RESET signal to the ispClock5600 to restart the PLL and resynchronize all the internal dividers.
RESET and Power-up Functions
To ensure proper PLL startup and synchronization of outputs, the ispClock5600 provides both internally generated
and user-controllable external reset signals. An internal reset is generated whenever the device is powered up. An
external reset may be applied by asserting a logic HIGH at the RESET pin. Please note that the RESET pin does
not have an internal pull-up or pull-down resistor associated with it and should be tied LOW if not used. Asserting
RESET resets all internal dividers, and will cause the PLL to lose lock. On losing lock, the VCO frequency will begin
dropping. The length of time required to regain lock is related to the length of time for which RESET was asserted.
• M divider setting
• N divider setting
• V divider settings
• PLL loop filter settings
• Output skew settings
• Internal feedback skew settings
• Internal vs. external feedback selection
• Input logic configuration
• Output bank logic configuration
• V-Divider to be used as feedback source
• Fine/Coarse skew mode selection
• UES string
– Logic family
– Input impedance
– Logic family
– V-Divider signal source
– Enable/SGATE control options
– Output impedance
– Slew rate
– Signal inversion
PS1
0
0
1
1
PS0
31
0
1
0
1
Active Profile
2
CMOS memory. Up to four independent con-
Profile 0
Profile 1
Profile 2
Profile 3
ispClock5600 Family Data Sheet