ISPPAC-POWR1014A LATTICE [Lattice Semiconductor], ISPPAC-POWR1014A Datasheet - Page 23

• Manufacturer Part Number: ISPPAC-POWR1014A
• Description: In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
I
I
devices on a circuit board. The ispPAC-POWR1014A supports a 7-bit addressing of the I
col, as well as SMBTimeout and SMBAlert features of the SMBus, enabling it to easily integrated into many types
of modern power management systems. Figure 14 shows a typical I
POWR1014As are slaved to a supervisory microcontroller. SDA is used to carry data signals, while SCL provides a
synchronous clock signal. The SMBAlert line is only present in SMBus systems. The 7-bit I
POWR1014A is fully programmable through the JTAG port.
Figure 14. ispPAC-POWR1014A in I
In both the I
ter device generates the SCL clock signal and coordinates all data transfers to and from a number of slave devices.
The ispPAC-POWR1014A is configured as a slave device, and cannot independently coordinate data transfers.
Each slave device on a given I
addressing portion of the standard. Any 7-bit address can be assigned to the ispPAC-POWR1014A device by pro-
gramming through JTAG. When selecting a device address, one should note that several addresses are reserved
by the I
compatibility. Table 6 lists these reserved addresses.
Table 6. I
2
2
C and SMBus are low-speed serial interface protocols designed to enable communications among a number of
C/SMBUS Interface (ispPAC-POWR1014A Only)
2
C and/or SMBus standards, and should not be assigned to ispPAC-POWR1014A devices to assure bus
2
C/SMBus Reserved Slave Device Addresses
SDA
V+
2
C and SMBus protocols, the bus is controlled by a single MASTER device at any given time. This mas-
0000 000
0000 000
0000 001
0000 010
0000 011
0000 1xx
0001 000
0001 100
0101 000
0110 111
1100 001
1111 0xx
1111 1xx
Address
MICROPROCESSOR
(I
2
SCL
C MASTER)
INTERRUPT
R/W bit
2
C bus is assigned a unique address. The ispPAC-POWR1014A implements the 7-bit
0
1
x
x
x
x
x
x
x
x
x
x
x
SDA/SMDAT (DATA)
SCL/SMCLK (CLOCK)
SMBALERT
2
C/SMBUS System
General Call Address
Start Byte
CBUS Address
Reserved
Reserved
HS-mode master code
NA
NA
NA
NA
NA
10-bit addressing
Reserved
I
2
C function Description
SDA
POWR1014A
(I
2
C SLAVE)
23
SCL
OUT5/
SMBA
2
General Call Address
Start Byte
CBUS Address
Reserved
Reserved
HS-mode master code
SMBus Host
SMBus Alert Response Address
Reserved for ACCESS.bus
Reserved for ACCESS.bus
SMBus Device Default Address
10-bit addressing
Reserved
C configuration, in which one or more ispPAC-
ispPAC-POWR1014/A Data Sheet
SMBus Function
SDA
POWR1014A
(I
2
C SLAVE)
SCL
2
C communications proto-
OUT5/
SMBA
2
C address of the
To Other
Devices
I
2
C