ISPPAC-POWR1014A LATTICE [Lattice Semiconductor], ISPPAC-POWR1014A Datasheet - Page 38

• Manufacturer Part Number: ISPPAC-POWR1014A
• Description: In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
The optional IDCODE (identification code) instruction is incorporated in the ispPAC-POWR1014/A and leaves it in
its functional mode when executed. It selects the Device Identification Register to be connected between TDI and
TDO. The Identification Register is a 32-bit shift register containing information regarding the IC manufacturer,
device type and version code (Figure 31). Access to the Identification Register is immediately available, via a TAP
data scan operation, after power-up of the device, or by issuing a Test-Logic-Reset instruction. The bit code for this
instruction is defined by Lattice as shown in Table 11.
Figure 31. ispPAC-POWR1014/A ID Code
ispPAC-POWR1014/A Specific Instructions
There are 25 unique instructions specified by Lattice for the ispPAC-POWR1014/A. These instructions are primarily
used to interface to the various user registers and the E
used to control or monitor other features of the device. A brief description of each unique instruction is provided in
detail below, and the bit codes are found in Table 11.
PLD_ADDRESS_SHIFT – This instruction is used to set the address of the PLD AND/ARCH arrays for subsequent
program or read operations. This instruction also forces the outputs into the OUTPUTS_HIGHZ.
PLD_DATA_SHIFT – This instruction is used to shift PLD data into the register prior to programming or reading.
This instruction also forces the outputs into the OUTPUTS_HIGHZ.
PLD_INIT_ADDR_FOR_PROG_INCR – This instruction prepares the PLD address register for subsequent
PLD_PROG_INCR or PLD_VERIFY_INCR instructions.
PLD_PROG_INCR – This instruction programs the PLD data register for the current address and increments the
address register for the next set of data.
PLD_PROGRAM – This instruction programs the selected PLD AND/ARCH array column. The specific column is
preselected by using PLD_ADDRESS_SHIFT instruction. The programming occurs at the second rising edge of
the TCK in Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAM_ENABLE
instruction). This instruction also forces the outputs into the OUTPUTS_HIGHZ.
PROGRAM_SECURITY – This instruction is used to program the electronic security fuse (ESF) bit. Programming
the ESF bit protects proprietary designs from being read out. The programming occurs at the second rising edge of
the TCK in Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAM_ENABLE
instruction). This instruction also forces the outputs into the OUTPUTS_HIGHZ.
PLD_VERIFY – This instruction is used to read the content of the selected PLD AND/ARCH array column. This
specific column is preselected by using PLD_ADDRESS_SHIFT instruction. This instruction also forces the outputs
into the OUTPUTS_HIGHZ.
DISCHARGE – This instruction is used to discharge the internal programming supply voltage after an erase or pro-
gramming cycle and prepares ispPAC-POWR1014/A for a read cycle. This instruction also forces the outputs into
the OUTPUTS_HIGHZ.
00145h = ispPAC-POWR1014A
10145h = ispPAC-POWR1014
0001 0000 0001 0100 0101 / 0000 0100 001 / 1
0000 0000 0001 0100 0101 / 0000 0100 001 / 1
MSB
Part Number
(20 bits)
Lattice Semiconductor
JEDEC Manufacturer
Identity Code for
(11 bits)
38
2
CMOS non-volatile memory. Additional instructions are
per 1149.1-1990
Constant 1
(1 bit)
LSB
ispPAC-POWR1014/A Data Sheet
(ispPAC-POWR1014)
(ispPAC-POWR1014A)