ISPPAC-POWR1014A LATTICE [Lattice Semiconductor], ISPPAC-POWR1014A Datasheet - Page 34

• Manufacturer Part Number: ISPPAC-POWR1014A
• Description: In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
inventory control data. The specifics of this feature are discussed in the IEEE 1149.1 serial interface section of this
data sheet.
Electronic Security
An electronic security “fuse” (ESF) bit is provided in every ispPAC-POWR1014/A device to prevent unauthorized
readout of the E
tional user bits in the device. This cell can only be erased by reprogramming the device, so the original configura-
tion cannot be examined once programmed. Usage of this feature is optional. The specifics of this feature are
discussed in the IEEE 1149.1 serial interface section of this data sheet.
Production Programming Support
Once a final configuration is determined, an ASCII format JEDEC file can be created using the PAC-Designer soft-
ware. Devices can then be ordered through the usual supply channels with the user’s specific configuration already
preloaded into the devices. By virtue of its standard interface, compatibility is maintained with existing production
programming equipment, giving customers a wide degree of freedom and flexibility in production planning.
Evaluation Fixture
Because the features of an ispPAC-POWR1014/A are all included in the larger ispPAC-POWR1220AT8 device,
designs implemented in an ispPAC-POWR1014/A can be verified using an ispPAC-POWR1220AT8 engineering
prototype board connected to the parallel port of a PC with a Lattice ispDOWNLOAD
strates proper layout techniques and can be used in real time to check circuit operation as part of the design pro-
cess. Input and output connections are provided to aid in the evaluation of the functionality implemented in ispPAC-
POWR1014/A for a given application. (Figure 28).
Figure 28. Download from a PC
IEEE Standard 1149.1 Interface (JTAG)
Serial Port Programming Interface Communication with the ispPAC-POWR1014/A is facilitated via an IEEE 1149.1
test access port (TAP). It is used by the ispPAC-POWR1014/A as a serial programming interface. A brief descrip-
tion of the ispPAC-POWR1014/A JTAG interface follows. For complete details of the reference specification, refer to
the publication, Standard Test Access Port and Boundary-Scan Architecture, IEEE Std 1149.1-1990 (which now
includes IEEE Std 1149.1a-1993).
Overview
An IEEE 1149.1 test access port (TAP) provides the control interface for serially accessing the digital I/O of the isp-
PAC-POWR1014/A. The TAP controller is a state machine driven with mode and clock inputs. Given in the correct
sequence, instructions are shifted into an instruction register, which then determines subsequent data input, data
output, and related operations. Device programming is performed by addressing the configuration register, shifting
data in, and then executing a program configuration instruction, after which the data is transferred to internal
E
2
CMOS cells. It is these non-volatile cells that store the configuration or the ispPAC-POWR1014/A. A set of
2
CMOS configuration bit patterns. Once programmed, this cell prevents further access to the func-
PAC-Designer
Software
34
ispDOWNLOAD
Cable (6')
4
ispPAC-POWR1014/A Data Sheet
ispPAC-POWR
Circuitry
System
1220AT8
Other
Device
®
cable. The board demon-