A54SX16-1CG256 ACTEL [Actel Corporation], A54SX16-1CG256 Datasheet
A54SX16-1CG256
Related parts for A54SX16-1CG256
A54SX16-1CG256 Summary of contents
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... Unique In-System Diagnostic and Debug Facility with Silicon Explorer • Software Design Support with Actel Designer and ® Libero Integrated Design Environment (IDE) Tools • Predictable, Technology Performance RT54SX16 (Obsolete) A54SX16 24,000 24,000 16,000 16,000 1,452 1,452 528 528 924 924 179 ...
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... SX Family FPGAs RadTolerant and HiRel Ordering Information RT54SX32 Part Number A54SX16 = 16,000 System Gates A54SX32 = 32,000 System Gates RT54SX16 = 16,000 System Gates – RadTolerant (Obsolete) RT54SX32 = 32,000 System Gates – RadTolerant (Obsolete) Product Plan RT54SX16 Devices 208-Pin Ceramic Quad Flat Pack (CQFP) ...
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... Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 Temperature and Voltage Derating Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 SX Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 A54SX16 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 RT54SX16 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 A54SX32 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24 RT54SX32 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26 Pin Description ...
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... This compatibility allows the user to prototype using the very low cost plastic package and then switch to the ceramic package for production. For more information on plastic packages, refer to the Family FPGAs datasheet. The A54SX16 and A54SX32 devices are manufactured using a 0.35 µ technology Semiconductor facility in Singapore ...
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SX Family FPGAs RadTolerant and HiRel Disclaimer All radiation performance information is provided for information purposes only and is not guaranteed. The total dose effects are lot-dependent, and Actel does not guarantee that future devices will continue to exhibit similar ...
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Logic Module Design The SX family architecture has been called a “sea-of- modules” architecture because the entire floor of the device is covered with a grid of logic modules with virtually no chip area lost to interconnect elements or routing ...
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SX Family FPGAs RadTolerant and HiRel Connect Figure 1-3 • R-Cell Figure 1-4 • C-Cell 1 -4 Routed Data Input S0 S1 PSETB Direct D Input HCLK CLRB CLKA CLKB CKS CKP ...
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Chip Architecture The SX family’s chip architecture provides a unique approach to module organization and chip routing that delivers the best register/logic mix for a wide variety of new and emerging applications. Module Organization Actel has arranged all C-cell and ...
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SX Family FPGAs RadTolerant and HiRel Routing Resources Clusters and SuperClusters can be connected through the use of two innovative local routing resources called FastConnect and DirectConnect that enable extremely fast and predictable interconnections of modules within Clusters and SuperClusters ...
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Type 2 SuperClusters Figure 1-7 • DirectConnect and FastConnect for Type 2 SuperClusters Clock Resources Actel’s high-drive routing structure provides three clock networks. The first clock, called HCLK, is hardwired from the HCLK buffer to the clock select MUX in ...
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... The antifuse architecture does not require active circuitry to hold a charge (as do SRAM or EPROM), making it the lowest-power architecture on the market. with dramatic Table 1-1 • Supply Voltages use complicated A54SX16 techniques such as A54SX32 RTSX16 RTSX32 Boundary Scan Testing (BST) All RTSX devices are IEEE 1149.1 (JTAG) compliant. They offer superior diagnostic and testing capabilities by providing BST and probing capabilities ...
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TDI TMS TCK TRST External Hardwired Pin Figure 1-10 • RTSX JTAG Circuitry Configuring Diagnostic Pins The JTAG and Probe pins (TDI, TCK, TMS, TDO, PRA, and PRB) are placed in the desired mode by selecting the appropriate check boxes ...
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SX Family FPGAs RadTolerant and HiRel Flexible Mode When the Reserve JTAG check box is cleared (the default setting in the Designer software), the RTSX is placed in flexible mode, which allows the TDI, TCK, and TDO pins to function ...
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... Serial Connection Figure 1-11 • Probe Setup Related Documents Datasheets 54SX Family FPGAs http://www.actel.com/documents/A54SXDS.pdf Application Notes Power-Up and Power-Down Behavior of 54SX and RT54SX Devices http://www.actel.com/documents/PowerUpAN.pdf ...
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SX Family FPGAs RadTolerant and HiRel 3 Operating Conditions Recommended Operating Conditions Table 1-3 • Absolute Maximum Ratings Symbol V DC Supply Voltage CCR V DC Supply Voltage CCA V DC Supply Voltage CCI V Input ...
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... IO I Standby Current Supply Current CC(D) CC(D) Dynamic CC Power-Up Sequencing Table 1-6 • RT54SX16, A54SX16, RT54SX32, A54SX32 V V CCA CCR 3.3 V 5.0 V Power-Down Sequencing Table 1-7 • RT54SX16, A54SX16, RT54SX32, A54SX32 V V CCA CCR 3.3 V 5.0 V Commercial Min. Max. (V – 0.1) V CCI CCI 2.4 V CCI 0.10 0.50 0.8 2 ...
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... Ceramic Quad Flat Pack (CQFP) Ceramic Quad Flat Pack (CQFP) RT54SX32 Ceramic Quad Flat Pack (CQFP) Ceramic Quad Flat Pack (CQFP) A54SX16 Ceramic Quad Flat Pack (CQFP) Ceramic Quad Flat Pack (CQFP) A54SX32 Ceramic Quad Flat Pack (CQFP) Ceramic Quad Flat Pack (CQFP and the junction-to-ambient air characteristic is θ ...
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... Equivalent capacitance values are shown in Table RT54SX16 C 7.0 EQM C 2.0 EQI C 10.0 EQO C 0.4 EQCR C 0.25 EQCD r 120 1 r 120 2 s 528 1 v2.1 SX Family FPGAs RadTolerant and HiRel active (dynamic) power dissipation CCA 1-9. A54SX16 RT54SX32 A54SX32 3.9 7.0 1.0 2.0 5.0 10.0 0.2 0.6 0.15 0.34 60 210 60 210 528 1,080 This EQ 1-3 3.9 1.0 5.0 0.3 0.23 107 107 1,080 1-15 ...
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... Fixed capacitance due to first routed array 1 clock r = Fixed capacitance due to second routed 2 array clock s = Fixed number of clock loads on the 1 dedicated array clock (528 for A54SX16 Equivalent capacitance of logic modules in EQM Equivalent capacitance of input buffers in pF EQI C = Equivalent capacitance of output buffers in ...
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... SUD = 0 0.0 ns Routed Clock t RCKH = 2.8 ns (100% Load) F MAX = 175 MHz Hardwired Clock t HCKH = 1 HMAX = 240 MHz Note: Values shown for A54SX16-1 at worst-case commercial conditions. Figure 1-12 • SX Timing Model Hardwired Clock External Setup = INY = 2.2 + 0.7 + 0.8 – 1.7 = 2.0 ns Clock-to-Out (Pin-to-Pin) ...
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SX Family FPGAs RadTolerant and HiRel 50% 50 Out 1 DLH t DHL Figure 1-13 • Output Buffer Delays Load 1 (Used to measure propagation delay) To the Output Under Test ...
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D t SUD CLK Q CLR PRESET Figure 1-17 • Register Cell Timing Characteristics – Flip-Flops Timing Characteristics Timing characteristics for SX devices fall into three categories: family-dependent, device-dependent, and design-dependent. The input characteristics are common to all SX family ...
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... SX Family FPGAs RadTolerant and HiRel A54SX16 Timing Characteristics Table 1-11 • A54SX16 (Worst-Case Military Conditions, V Parameter Description 1 C-Cell Propagation Delays t Internal Array Module PD 2 Predicted Routing Delays Routing Delay, Direct Connect Routing Delay, Fast Connect Routing Delay ...
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... Table 1-12 • A54SX16 (Worst-Case Military Conditions, V Parameter Description I/O Module – TTL Output Timing* t Data-to-Pad LOW to HIGH DLH t Data-to-Pad HIGH to LOW DHL t Enable-to-Pad LOW ENZL t Enable-to-Pad HIGH ENZH t Enable-to-Pad, LOW to Z ENLZ t Enable-to-Pad, HIGH to Z ...
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SX Family FPGAs RadTolerant and HiRel RT54SX16 Timing Characteristics Table 1-13 • RT54SX16 (Worst-Case Military Conditions, V Parameter Description 1 C-Cell Propagation Delays t Internal Array Module PD 2 Predicted Routing Delays Routing Delay, Direct Connect ...
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Table 1-14 • RT54SX16 (Worst-Case Military Conditions, V Parameter Description I/O Module – TTL Output Timing* t Data-to-Pad LOW to HIGH DLH t Data-to-Pad HIGH to LOW DHL t Enable-to-Pad LOW ENZL t Enable-to-Pad HIGH ENZH ...
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SX Family FPGAs RadTolerant and HiRel A54SX32 Timing Characteristics Table 1-15 • A54SX32 Timing Characteristics (Worst-Case Military Conditions, V Parameter Description 1 C-Cell Propagation Delays t Internal Array Module PD 2 Predicted Routing Delays Routing Delay, ...
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Table 1-16 • A54SX32 Timing Characteristics (Worst-Case Military Conditions, V Parameter Description I/O Module – TTL Output Timing* t Data-to-Pad LOW to HIGH DLH t Data-to-Pad HIGH to LOW DHL t Enable-to-Pad LOW ENZL t Enable-to-Pad ...
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SX Family FPGAs RadTolerant and HiRel RT54SX32 Timing Characteristics Table 1-17 • RT54SX32 Timing Characteristics (Worst-Case Military Conditions, V Parameter Description 1 C-Cell Propagation Delays t Internal Array Module PD 2 Predicted Routing Delays Routing Delay, ...
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Table 1-18 • RT54SX32 Timing Characteristics (Worst-Case Military Conditions, V Parameter Description I/O Module – TTL Output Timing* t Data-to-Pad LOW to HIGH DLH t Data-to-Pad HIGH to LOW DHL t Enable-to-Pad LOW ENZL t Enable-to-Pad ...
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SX Family FPGAs RadTolerant and HiRel Pin Description CLKA/B Clock A and B These pins are clock inputs for clock distribution networks. Input levels are compatible with standard TTL, LVTTL, 3.3 V PCI, or 5.0 V PCI specifications. The clock ...
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Package Pin Assignments 208-Pin CQFP 208 207 206 205 204 203 202 201 200 Pin #1 Index Figure 2-1 • 208-Pin CQFP (Top ...
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... I/O I/O 53 I/O I/O 54 I/O I/O 55 I/O I/O 56 I/O I/O 57 I/O I/O 58 I/O I/O 59 I/O I CCR CCR GND GND CCA CCA GND GND 64 I/O I/O 65 I/O TRST 66 I/O I/O 67 I/O I/O 68 I/O I/O 69 I/O I/O 70 I/O I/O 71 I/O I/O 72 v2.1 208-Pin CQFP A54SX16 RT54SX16 A54SX32 RT54SX32 Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I CCI CCI CCI CCA CCA CCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND I/O I/O I/O I/O I/O I/O ...
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... V V 134 CCI CCI I/O I/O 135 I/O I/O 136 I/O I/O 137 I/O I/O 138 TDO, I/O TDO, I/O 139 I/O I/O 140 GND GND 141 I/O I/O 142 I/O I/O 143 I/O I/O 144 v2.1 SX Family FPGAs RadTolerant and HiRel 208-Pin CQFP A54SX16 RT54SX16 A54SX32 RT54SX32 Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I CCA CCA CCA CCI CCI CCI I/O I/O I/O I/O I/O ...
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... CCI CCI I/O I/O 201 I/O I/O 202 I/O I/O 203 I/O I/O 204 I/O I/O 205 I/O I/O 206 I/O I/O 207 I/O I/O 208 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CLKA CLKA v2.1 208-Pin CQFP A54SX16 RT54SX16 A54SX32 RT54SX32 Function Function Function CLKB CLKB CLKB CCR CCR CCR GND GND GND CCA CCA CCA GND GND GND PRA, I/O PRA, I/O PRA, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...
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CQFP 256 255 254 253 252 251 250 249 248 Pin #1 Index Figure 2-2 • 256-Pin CQFP (Top View) 200 199 ...
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... I/O I/O 53 I/O I/O 54 I/O I/O 55 I/O I/O 56 I/O I/O 57 I/O I/O 58 I/O I/O 59 I/O I/O 60 I/O I/O 61 I/O I/O 62 I/O I/O 63 I/O I CCI CCI GND GND CCA CCA GND GND 68 I/O I/O 69 I/O I/O 70 I/O TRST 71 I/O I/O 72 I/O I/O 73 I/O I/O 74 v2.1 256-Pin CQFP A54SX16 RT54SX16 A54SX32 RT54SX32 Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I CCA CCA CCA I/O I/O I I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O GND ...
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... HCLK HCLK 133 I/O I/O 134 I/O I/O 135 I/O I/O 136 I/O I/O 137 I/O I/O 138 I/O I/O 139 I/O I/O 140 I/O I/O 141 I/O I/O 142 I/O I/O 143 I/O I/O 144 I/O I/O 145 I/O I/O 146 GND GND 147 I/O I/O 148 v2.1 SX Family FPGAs RadTolerant and HiRel 256-Pin CQFP A54SX16 RT54SX16 A54SX32 RT54SX32 Function Function Function I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I I/O TDO, I/O TDO, I/O TDO, I/O ...
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... I/O I/O 207 I/O I/O 208 I/O I/O 209 I/O I/O 210 V V 211 CCA CCA GND GND 212 GND GND 213 I/O I/O 214 I/O I/O 215 I/O I/O 216 I/O I/O 217 I/O I/O 218 I/O I/O 219 I/O I/O 220 I/O I/O 221 I/O I/O 222 v2.1 256-Pin CQFP A54SX16 RT54SX16 A54SX32 RT54SX32 Function Function Function I/O I/O I I/O I/O I/O I/O GND GND GND I/O I I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O ...
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... CQFP Pin A54SX16 RT54SX16 Number Function Function 223 V V CCR CCR 224 GND GND 225 PRA, I/O PRA, I/O 226 I/O I/O 227 NC NC 228 I/O I/O 229 I/O I/O 230 I/O I/O 231 I/O I/O 232 NC NC 233 I/O I/O 234 I/O I/O 235 I/O I/O 236 NC NC 237 I/O I/O 238 I/O I/O 239 NC NC 240 GND GND 241 I/O I/O 242 ...
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Datasheet Information List of Changes The following table lists critical changes that were made in the current version of the document. Previous Version Changes in Current Version ( v2.0 The "Product Profile" The "Ordering Information" The "Product Plan" ...
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... SX Family FPGAs RadTolerant and HiRel Datasheet Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Datasheet Supplement." The definitions of these categories are as follows: ...
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Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. Actel Corporation Actel Europe Ltd. 2061 Stierlin Court Dunlop House, Riverside Way Mountain View, CA Camberley, Surrey GU15 3YL 94043-4655 ...