A54SX16-1CG256 ACTEL [Actel Corporation], A54SX16-1CG256 Datasheet - Page 11

• Manufacturer Part Number: A54SX16-1CG256
• Description: SX Family FPGAs RadTolerant and HiRel
• Manufacturer: ACTEL [Actel Corporation]

Figure 1-7 • DirectConnect and FastConnect for Type 2 SuperClusters
Clock Resources
Actel’s high-drive routing structure provides three clock
networks. The first clock, called HCLK, is hardwired from
the HCLK buffer to the clock select MUX in each R-cell.
HCLK cannot be connected to combinational logic. This
provides a fast propagation path for the clock signal,
enabling
performance of the RTSX devices. The hardwired clock is
tuned to provide clock skew is less than 0.5 ns worst case.
The remaining two clocks (CLKA and CLKB) are global
clocks that can be sourced from external pins or from
internal logic signals within the RTSX device. CLKA and
CLKB may be connected to sequential cells or to
combinational logic. If CLKA or CLKB is sourced from
internal logic signals, then the external clock pin cannot
be used for any other input and must be tied low or
high.
constant load HCLK.
CLKB circuit used in all RTSX devices with the exception
of the RT54SX72S device.
Figure 1-8
the
describes the clock circuit used for the
8.9
Figure 1-9
Type 2 SuperClusters
ns
clock-to-out
describes the CLKA and
(pad-to-pad)
v2.1
Figure 1-8 • RTSX Constant Load Clock Pad
Figure 1-9 • RTSX Clock Pads
SX Family FPGAs RadTolerant and HiRel
DirectConnect
• No Antifuses
FastConnect
• One Antifuse
Routing Segments
• Typically Two Antifuses
• Max. Five antifuses
HCLKBUF
CLKBUF
CLKBUFI
CLKINT
CLKINTI
Constant Load
Clock Network
From Internal Logic
Clock Network
1-7