A54SX16-1CG256 ACTEL [Actel Corporation], A54SX16-1CG256 Datasheet - Page 21

• Manufacturer Part Number: A54SX16-1CG256
• Description: SX Family FPGAs RadTolerant and HiRel
• Manufacturer: ACTEL [Actel Corporation]

Temperature and Voltage Derating Factors
Table 1-10 • Temperature and Voltage Derating Factors
SX Timing Model
Note:
Figure 1-12 • SX Timing Model
Hardwired Clock
V
3.0
3.3
3.6
External Setup
Clock-to-Out (Pin-to-Pin)
CCA
Hardwired
Clock
Routed
Clock
Values shown for A54SX16-1 at worst-case commercial conditions.
(Normalized to Worst-Case Commercial, T
I/O Module
F HMAX = 240 MHz
F MAX = 175 MHz
t HCKH = 1.3 ns
t RCKH = 2.8 ns (100% Load)
Input Delays
0.78
0.73
0.69
–40
=
=
=
=
t
INY = 2.2 ns
t
2.2 + 0.7 + 0.8 – 1.7 = 2.0 ns
t
1.7 + 0.6 + 0.7 + 2.8 = 5.8 ns
INY
HCKH
t SUD = 0.8 ns
t HD = 0.0 ns
+ t
+ t
IRD1
RCO
t IRD2 = 1.2 ns
+ t
0.87
0.82
0.77
+ t
SUD
0
Register Cell
t RCO = 0.6 ns
RD1
D
– t
+ t
HCKH
Q
DHL
Combinatorial Cell
J
Internal Delays
= 70°C, V
t PD = 0.9 ns
t RD1 = 0.7 ns
Junction Temperature (T
0.89
0.83
0.78
v2.1
25
CCA
Routed Clock
External Setup
Clock-to-Out (Pin-to-Pin)
Register Cell
= 3.0 V)
t RCO = 0.6 ns
D
t RD1 = 0.7 ns
t RD4 = 2.2 ns
t RD8 = 4.3 ns
Predicted
Q
Routing
Delays
1.00
0.93
0.87
70
t RD1 = 0.7 ns
SX Family FPGAs RadTolerant and HiRel
J
)
I/O Module
=
=
=
=
Output Delays
t DLH = 2.8 ns
t ENZH = 2.8 ns
I/O Module
t
2.2 + 0.7 + 0.8 – 2.4 = 1.3 ns
t
2.4 + 0.6 + 0.7 + 2.8 = 6.5 ns
1.04
0.97
0.92
INY
RCKH
85
t DHL = 2.8 ns
+ t
+ t
IRD1
RCO
+ t
+ t
SUD
RD1
1.16
1.08
1.02
125
– t
+ t
RCKH
DHL
1-17