A54SX16-1CG256 ACTEL [Actel Corporation], A54SX16-1CG256 Datasheet - Page 13

• Manufacturer Part Number: A54SX16-1CG256
• Description: SX Family FPGAs RadTolerant and HiRel
• Manufacturer: ACTEL [Actel Corporation]

Figure 1-10 • RTSX JTAG Circuitry
Configuring Diagnostic Pins
The JTAG and Probe pins (TDI, TCK, TMS, TDO, PRA, and
PRB) are placed in the desired mode by selecting the
appropriate check boxes in the Variation dialog
window. This dialog window is accessible through the
Design Setup Wizard under the Tools menu in the Actel
Designer software.
TRST Pin
The TRST pin functions as a Boundary Scan Reset pin. The
TRST pin is an asynchronous, active-low input to initialize
or reset the BST circuit. An internal pull-up resistor is
automatically enabled on the TRST pin.
Hardwired Pin
TRST External
TMS
TCK
TDI
Instruction Register (IR)
Clocks and/or Controls
Data Registers (DRs)
TAP Controller
v2.1
Dedicated Test Mode
When the Reserve JTAG check box is selected in the
Designer software, the RTSX is placed in Dedicated Test
mode, which configures the TDI, TCK, and TDO pins for
BST or in-circuit verification with Silicon Explorer II. An
internal pull-up resistor is automatically enabled on both
the TMS and TDI pins. In dedicated test mode, TCK, TDI,
and TDO are dedicated test pins and become unavailable
for pin assignment in the Pin Editor. The TMS pin will
function as specified in the IEEE 1149.1 (JTAG)
Specification.
SX Family FPGAs RadTolerant and HiRel
0
1
Output
Stage
TDO
1-9