A54SX16-1CG256 ACTEL [Actel Corporation], A54SX16-1CG256 Datasheet - Page 29

• Manufacturer Part Number: A54SX16-1CG256
• Description: SX Family FPGAs RadTolerant and HiRel
• Manufacturer: ACTEL [Actel Corporation]

Table 1-16 • A54SX32 Timing Characteristics
Parameter
I/O Module – TTL Output Timing*
t
t
t
t
t
t
d
d
Dedicated (Hardwired) Array Clock Network
t
t
t
t
t
t
f
Routed Array Clock Networks
t
t
t
t
t
t
t
t
t
t
t
Note: *Delays based on 35 pF loading, except t
DLH
DHL
ENZL
ENZH
ENLZ
ENHZ
HCKH
HCKL
HPWH
HPWL
HCKSW
HP
HMAX
RCKH
RCKL
RCKH
RCKL
RCKH
RCKL
RPWH
RPWL
RCKSW
RCKSW
RCKSW
TLH
THL
(Worst-Case Military Conditions, V
Data-to-Pad LOW to HIGH
Data-to-Pad HIGH to LOW
Enable-to-Pad, Z to LOW
Enable-to-Pad, Z to HIGH
Enable-to-Pad, LOW to Z
Enable-to-Pad, HIGH to Z
Delta LOW to HIGH
Delta HIGH to LOW
Input LOW to HIGH
Input HIGH to LOW
Minimum Pulse Width HIGH
Minimum Pulse Width LOW
Maximum Skew
Minimum Period
Maximum Frequency
Input LOW to HIGH (Light Load)
Input HIGH to LOW (Light Load)
Input LOW to HIGH (50% Load)
Input HIGH to LOW (50% Load)
Input LOW to HIGH (100% Load)
Input HIGH to LOW (100% Load)
Minimum Pulse Width HIGH
Minimum Pulse Width LOW
Maximum Skew (Light Load)
Maximum Skew (50% Load)
Maximum Skew (100% Load)
(Pad to R-Cell Input)
(Pad to R-Cell Input)
(Pad to R-Cell Input)
(Pad to R-Cell Input)
(Pad to R-Cell Input)
(Pad to R-Cell Input)
(Pad to R-Cell Input)
(Pad to R-Cell Input)
Description
ENZL
CCR
and t
= 4.75 V, V
ENZH
. For t
v2.1
CCA
ENZL
Min.
, V
2.1
2.1
4.2
3.1
3.1
and t
CCI
'–1' Speed
= 3.0 V, T
ENZH
the loading is 5 pF.
Max.
0.05
0.05
240
2.8
2.8
2.3
2.8
4.5
2.2
1.7
1.9
0.4
2.4
2.7
2.9
2.9
2.8
2.9
0.6
0.8
0.8
J
= 125°C)
SX Family FPGAs RadTolerant and HiRel
Min.
2.4
2.4
4.8
3.7
3.7
'Std' Speed
Max.
0.06
0.08
205
3.3
3.3
2.8
3.3
5.2
2.6
2.0
2.2
0.4
2.9
3.1
3.3
3.5
3.3
3.5
0.8
0.9
0.9
Units
ns/pF
ns/pF
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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