UPD64084 NEC, UPD64084 Datasheet
UPD64084
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UPD64084 Summary of contents
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... The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. S16021EJ2V0DS00 (2nd edition) ...
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PIN CONFIGURATION (TOP VIEW) 100-pin plastic LQFP (fine pitch) (14 PD64084GC-8EA-A PD64084GC-8EA-Y DGND 1 TESTIC1 2 TESTIC2 3 TEST01 4 TEST02 5 TEST03 6 TEST04 7 TEST05 8 TEST06 9 TEST07 10 TEST08 11 TEST09 12 EXTALTF 13 EXTDYCO0 14 ...
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PIN NAME ACO : Analog C (Chroma) Signal Output AGND : Analog Section Ground ALTF : Alternate Flag for Digital YC Output AVDD : Analog Section Power Supply AYI : Analog Composite Signal Input AYO : Analog Y (Luma) Signal ...
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BLOCK DIAGRAM 10-bit Digital Comp. Input 10-bit Clamp Comp. Input ADC 4f 8f PLL SC 8f BPF 8-bit f DAC SC f /227. MHz Dec. Ext. Sync. Sync. Separate Separate Generator 4 4-Mbit Frame Memory C C ...
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TERMINOLOGY This manual use the abbreviation listed below: ADC : A/D (Analog to Digital) converter DAC : D/A (Digital to Analog) converter LPF : Low-pass filter BPF : Band-pass filter Y signal, or Luma : Luminance, or luminance signal C ...
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... Start-up of Power Supply and Reset.............................................................................................................13 3. VIDEO SIGNAL INPUT BLOCK ............................................................................................................................14 3.1 Video Signal Inputs .......................................................................................................................................14 3.2 Pedestal Level Reproduction ........................................................................................................................14 3.3 Video Signal Input Level ...............................................................................................................................15 3.4 Pin Treatment................................................................................................................................................15 3.5 External ADC Connection Method ................................................................................................................16 4. CLOCK/TIMING GENERATION BLOCK...............................................................................................................17 4.1 Sync Separator and Timing Generator .........................................................................................................17 4.2 Composite Sync Signal Input........................................................................................................................17 4.3 Horizontal/Burst Phase Detection Circuit......................................................................................................17 4.4 PLL Filter Circuit ...........................................................................................................................................17 4 ...
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... Pin Treatment .............................................................................................................................................. 30 14. DIGITAL CONNECTION WITH GHOST REDUCER IC 14.1 Outline ......................................................................................................................................................... 31 14.2 System Configuration and Control Method.................................................................................................. 33 14.2.1 Selecting video signal input path...................................................................................................... 33 14.2.2 Selecting mode according to clock and video signal input path ....................................................... 33 14.3 Setting of Digital Direct-Connected System ................................................................................................ 34 14.3.1 Hardware setting .............................................................................................................................. 34 14.3.2 Register setting ................................................................................................................................ BUS INTERFACE............................................................................................................................................. 36 15.1 Basic Specification ...................................................................................................................................... 36 15 ...
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ELECTRICAL CHARACTERISTICS .....................................................................................................................57 17. APPLICATION CIRCUIT EXAMPLE .....................................................................................................................62 18. PACKAGE DRAWING............................................................................................................................................63 19. RECOMMENDED SOLDERING CONDITIONS.....................................................................................................64 8 Data Sheet S16021EJ2V0DS PD64084 ...
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... PD: bus slave address selection input (L : B8h / B9h BAh / BBh bus clock input (Connected to system SCL line bus data input/output (Connected to system SDA line generator DAC section ground generator DAC section 2.5 V supply voltage SC 2 ...
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No. Symbol I/O Level 57 CLK8 I/O LVTTL 3-state 58 RSTB I Schmitt 59 ST0 O LVTTL 60 ST1 O LVTTL 61 NSTD O LVTTL 63- DYCO0- I/O LVTTL 72 DYCO9 3-state 73 ALTF O LVTTL 74 LINE I LVTTL ...
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SYSTEM OVERVIEW 2.1 Operation Modes The PD64084 can operate in the following major four signal processing modes. Mode selection is performed according to NRMD on the serial bus. Note Serial bus setting Function Mode name NRMD = 0 Y/C ...
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Filter Processing Table 2-2 lists filters used in each mode. Mode Standard / nonstandard / killer signal detection YCS mode Standard signal detected (NRMD = 0) Nonstandard signal detected Killer signal detected YCS+ mode Standard or horizontal (NRMD = ...
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... Power ON 3.3 V start-up 3.3 V DVDDIO 0 V 2.5 V start-up 2.5 V DVDD 0 V 3.3 V RSTB Don't care 0 V Caution Reset is always necessary whether using the serial bus register or not Bus Interface Reset Sequence RSTB='L' RSTB=' MIN. 100 s MIN bus access disable I C bus access enable ...
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... LSB levels, and outputs the feedback level. This output signal is connected to VCLY pin via internal resistor to feed back to video signal for fixing pedestal level to 256 LSB. Pull down the VCLY pin via a 0.1 F bypass capacitor and electrolysis capacitor for loop filter ...
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... Video Signal Input Level It is necessary to limit the level of video (composite) signal inputs to within a certain range to cope with the maximum amplitude of the video signal and variations in it. Figure 3-2 shows the waveform of the video signal input whose amplitude is 140 IRE = 820 LSB (0.8 times a maximum input range of 1024 LSB). In this case possible to input a ...
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... External ADC Connection Method Setting up EXADINS = 1 on the serial bus puts the IC in the external ADC mode. In this mode, the ALTF pin is used to output 4f sampling clock pulses, and the DYCO9 to DYCO0 pins are used to receive digital data inputs. Setting up SC ST0S = 01 on the serial bus causes a clamp pulse to be output from the ST0 pin used as a pedestal clamp pulse for external ADC. The clamp potential for the pedestal level of external ADC must be determined so that the sampled value becomes about 256 ± ...
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CLOCK/TIMING GENERATION BLOCK This block generates system clock pulses and timing signals from video signals. Figure 4-1. Clock/Timing Generation Block Diagram System clock (8f System clock (4f Composite sync signal System timing Sync. CSI Timing generator separator Sync. AYI ...
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... DAC to an analog sine waveform before it is output from the SC FSCO pin. Because this output contains harmonic components, they must be removed using an external band-pass filter (BPF) connected via a buffer, before the analog sine waveform is input to the FSCI pin via a capacitor. The f generator uses a 20 MHz free-run clock pulse as a reference. 4.7 ...
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COMB FILTER BLOCK This block performs Y/C separation or frame comb type YNR according to the result of checks in various detection circuits. Figure 5-1. Comb Filter Block Diagram Composite Delay input Line comb filter H ...
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MOTION DETECTION BLOCK This block generates a 4-bit motion factor indicating an inter-frame motion level from the video signal inter-frame difference. This motion factor is used as a mixture ratio to indicate how the frame and line comb filter ...
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YNR/CNR BLOCK This block performs frame recursive YNR and CNR used in the YCS+ mode. Y signal input Current signal input H Demodulation 1H Previous frame Y 526H 1H Previous frame C 526H Frame ...
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NONSTANDARD SIGNAL DETECTION BLOCK This block detects nonstandard signals not conforming to the NTSC standard, such as VCR playback signals, home TV game signals, and Laser-Disc special playback signals. The detection result is used to stop inter-frame video processing. ...
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WCV-ID DECODER / ID-1 DECODER BLOCK This block decodes ID-1 signal of 20H/283H and an identification control signal superimposed on a wide clear vision signal of 22H and 285H (The wide clear vision standard applies only in Japan). 9.1 ...
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ID-1 Decoder The ID-1 decoder checks whether the video signal contains an ID-1 signal by examining mainly the following five items. If all these items turn out to be normal signal is detected. <1> A difference of ...
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Y SIGNAL OUTPUT PROCESSING BLOCK After Y/C separation or Y Noise reduction, this block performs high-frequency coring, peaking, and vertical aperture compensation for the Y signal submitted to YNR processing. Figure 10-1. Y Signal Output Processing Block Diagram ID1ENW0A1 ...
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Y Peaking Filter Circuit The Y peaking filter circuit performs peaking processing for the Y signal to correct the frequency response of the Y signal. <1> BPF circuit : Extracts high-frequency components from the original Y signal according to ...
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C SIGNAL OUTPUT PROCESSING BLOCK After Y/C separation, the C signal output processing block performs delay adjustment, BPF processing, and gain adjustment for the C signal submitted to CNR processing. Figure 11-1. C Signal Output Processing Block Diagram C ...
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VIDEO SIGNAL OUTPUT BLOCK The video signal output block can convert digital video signals to analog form. It can also output digital video signals without performing D/A conversion. Figure 12-1. Video Signal Output Block Diagram Digital YC / alternate ...
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... Pull down the CBPY and CBPC pins via a 0.1 F bypass capacitor. When DAC aren't used, connect AGND pin to digital ground, AVDD pin to digital power supply, and AYO, ACO, CBPY and CBPC pins set open. When the digital I/O pin DYCO9 to DYCO0 aren't used, these pins set open. ...
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EXTEND DIGITAL INPUT / OUTPUT This device have the extend digital I/O terminals EXTDYCO9-EXTDYCO0 in addition to DYCO9-DYCO0. Using these terminals, the digital in to digital out system is available. Table 13-1. Mode setting for extend digital I/O terminals ...
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... PD64084 can perform processing from ghost reduction to three-dimension Y/C separation digitally in 10-bit units when it is directly connected to NEC Electronics' ghost reducer IC PD64031A. Figure 14-1 shows the system configuration when the PD64031A and PD64084 are digitally connected directly. 14.1 Outline When signals are input from a ground wave tuner, the composite video signal is first input to the A/D converter of the PD64031A, where the ghost of the signal is reduced ...
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... When signals are input from video (composite or S input), the directly input to the A/D converter of the PD64084 (see Figure 14-2). Figure 14-2. Example of Digital Connection System without Ghost Reducer (when signals are input from external source) C sync separation ADC Digital GR filter clamp amplifier Delay ...
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... Selecting mode according to clock and video signal input path When the PD64031A and PD64084 are digitally connected directly, the system clock must be shared by the two ICs. When the ghost reducer is used (when signals are input from a tuner), the PD64031A generates burst lock clock shown in Figure 14-1 ...
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... Setting of Digital Direct-Connected System 14.3.1 Hardware setting See the pin connection and setting in the following table to digitally connect the PD64031A and PD64084 directly. Table 14-1. Pin Setting for Digital Direct-Connection PD64031A Pin Signal Direction DO9 to DO0 (pins 6 to 15) N3D (pin 3) CSO (pin 4) ALTF (pin 5) ...
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... Register setting Correctly set the following registers when digitally connecting the PD64031A and PD64084 directly. Also refer to the following table for register setting to specify whether the ghost reducer is used or not. Register With Ghost Reducer Used PD64031A EXDAS (SA01h: D7) N3D1STEN (SA01h: D5) ...
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I C BUS INTERFACE 15.1 Basic Specification 2 The I C bus is a two-wire bi-directional serial bus developed by Philips. It consists of a serial data line (SDA) for communication between ICs and a serial clock line ...
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Data Transfer Formats Immediately when the master IC satisfies the start condition, each slave receives a slave address. If the received slave address matches that of a slave IC, communication begins between the slave IC and the master IC. ...
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Read mode format (transmission mode for slaves slave IC receives its read-mode slave address in byte 1, it sends data in byte 2 and the subsequent bytes. No subaddress is specified in this mode. Transmission begins always ...
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... FSCFG 13 HSSL 14 BGPS 15 ADCLKS ADPDS 16 SYSPDS EXTDYCO 17 CNROFS HCNTFSYN ADCLPFSW Caution It may be necessary to change set values on the serial bus depending on the results of performance evaluation conducted by NEC Electronics. Data Map (SA00-SA17 COUTS NSDS MSS MFREEZE PECS HDP YNRLIM CNRK CNRINV ...
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Read register mapping Slave address: 10111001b = B9h (SLA0 = L), 10111011b = BBh (SLA0 = VER 01 02 ED2 B3 03 B10 B11 DCLEVH CRCCH DCFEL 40 Data ...
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... Serial Bus Register Functions Table 15-2 lists the function of each write register. The initial and typical values for each register were determined for evaluation purposes by NEC Electronics. They are not necessarily optimum values. (1) Write Register Table 15-2. Write Register Functions (1/14) SA Bit Name and function ...
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Table 15-2. Write Register Functions (2/14) SA Bit Name and function 01 D7-D6 CLKS Specifies whether to force use of the system clock. D5-D4 NSDS Specifies whether to force standard/nonstandard signal processing. D3-D2 MSS Specifies whether to force inter-frame or ...
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Table 15-2. Write Register Functions (3/14) SA Bit Name and function 02 D7-D6 DYCOS Specifies DYCO pin input/output. D5 EXADINS Specifies whether to select external ADC. D4 MFREEZE External memory test bit D3-D2 PECS Specifies a pedestal error correction test ...
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Table 15-2. Write Register Functions (4/14) SA Bit Name and function 04 D7-D4 DYCOR DY detection coring level (Y motion detection coring) D3-D0 DYGAIN DY detection gain (Y motion detection gain) 05 D7-D4 DCCOR DC detection coring level (C motion ...
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Table 15-2. Write Register Functions (5/14) SA Bit Name and function 06 D7 YNRK Specifies the frame recursive YNR nonlinear filter gain. D6 YNRINV Specifies the frame recursive YNR nonlinear filter convergence level. D5-D4 YNRLIM Specifies the frame recursive YNR ...
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Table 15-2. Write Register Functions (6/14) SA Bit Name and function 07 D7 ID1ENON Specifies whether to superimpose ID-1 specification ID signal. D6 ID1ENW0A1 Specifies whether to set bit A1 of ID-1 word 0. D5 ID1ENW0A2 Specifies whether to set ...
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Table 15-2. Write Register Functions (7/14) SA Bit Name and function 08 D7-D6 WSC Specifies the amount of noise detection coring. D5-D4 VTRH Specifies hysteresis for horizontal sync nonstandard signal detection (out-of- horizontal sync intra-field) D3-D2 VTRR Specifies sensitivity for ...
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Table 15-2. Write Register Functions (8/14) SA Bit Name and function 09 D7 WSS Specifies the pre-filter characteristic of noise detection. D6 ID1DECON ID-1 decoder D5-D4 TH ID-1 decorder check level D3 FELCHK ID-1 decoder Field check enable D2-D1 TT ...
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Table 15-2. Write Register Functions (9/14) SA Bit Name and function 0B D7 TEST Test bit D6 TEST Test bit D5-D4 YPFT Specifies the Y peaking filter (BPF) center frequency. D3-D0 YPFG Specifies a Y peaking filter gain. Description 0: ...
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Table 15-2. Write Register Functions (10/14) SA Bit Name and function 0C D7-D6 V1PSEL Line comb filter horizontal dot interference suppression level D5-D4 VEGSEL Line comb filter vertical dot interference suppression level D3 CC3N Selects a line comb filter C ...
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Table 15-2. Write Register Functions (11/14) SA Bit Name and function 10 D7-D6 YHCOR Specifies Y output high frequency component coring. D5 YHCGAIN Specifies Y output high- frequency component coring gain. D4 ED2OFF Specifies WCV-ID detection circuit. D3 OVST Nonstandard ...
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Table 15-2. Write Register Functions (12/14) SA Bit Name and function 11 D7 SHT1 Nonstandard signal detection test bit D6 SHT0 Nonstandard signal detection test bit D5 VCT counter test bit D4 OTT counter ...
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Table 15-2. Write Register Functions (13/14) SA Bit Name and function 14 D7-D4 BGPS Specifies the internal burst gate start position. D3-D0 BGPW Specifies the internal burst gate width. 15 D7-D6 ADCLKS Specifies the ADC clock delay. D5 ADPDS Specifies ...
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Table 15-2. Write Register Functions (14/14) SA Bit Name and function 16 D7-D6 SYSPDS System power down D5 EXTDYCO Extended digital I/O enable D4 HIZEN Digital input / output status select D3 VLSEL Test bit D2 VLTYPE Test bit D1 ...
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Read Register Table 15-3. Read Register Functions (1/2) SA Bit Name and function 00 D7-D6 VER Product Version Code KILF Killer detection flag D3 NSDF Horizontal sync signal detection flag D2 LDSDF Frame sync nonstandard signal ...
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Table 14-3. Read Register Functions (2/2) SA Bit Name and function 06 D7 DCLEVH ID-1 Decode Reference signal detect D6 CRCCH ID-1 Decode CRC check D5 DCFEL ID-1 Decode Reference signal Field check D4 CRCCFEL ID-1 Decode CRC field check ...
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ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (T = +25 C Unless otherwise specified) A Parameter Symbol Digital section supply voltage DV DD Analog section supply voltage AV DD DRAM section supply voltage DV DDRAM I/O section supply voltage DV DDIO ...
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Digital Section DC Characteristics ( 2.5 ±0 3.3 ±0.3 V, DGND = DGNDRAM = DDRAM DDIO Parameter Symbol Digital section current drain DDRAM DI DDIO Input leakage ...
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Analog Section DC Characteristics (AV = 2.5 ±0.2 V, AGND = +25 C Unless otherwise specified Parameter Symbol Analog section current drain AI DD ADC resolution RES ADY ADC integral linearity error ILE ADY ...
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Digital Section AC Characteristics ( 2.5 ±0 DDRAM DDIO +70°C) A Parameter Symbol Video data output delay t D:DAT Internal signal monitor output t D:STAT delay CSI input set-up time ...
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Clock and Timing Generation Section AC Characteristics ( 2.5 ±0 DDRAM 70°C) A Parameter Symbol Subcarrier output frequency f FSCO Subcarrier output amplitude V FSCO Clock ...
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APPLICATION CIRCUIT EXAMPLE 0 Clock mode (GND) 8f clock output SC States 0 [VD, etc.] States 1 [HD, etc.] Non standard detection Digital Y input Ext. ADC clock C-sync. input Forced 2D Killer input (option) Caution This ...
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PACKAGE DRAWING 100-PIN PLASTIC LQFP (FINE PITCH) (14x14 100 NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum material condition ...
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... RECOMMENDED SOLDERING CONDITIONS The PD64084 should be solderd and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, content an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Table 19-1 ...
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... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...
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... NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others ...