UPD64084 NEC, UPD64084 Datasheet - Page 53

• Manufacturer Part Number: UPD64084
• Description: THREE-DIMENSIONAL Y/C SEPARATION LSI WITH ON-CHIP MEMORY
• Manufacturer: NEC

14
15
SA
D7-D4
D3-D0
D7-D6
D5
D4
D3
D2
D1-D0
Bit
BGPS
Specifies the internal
burst gate start position.
BGPW
Specifies the internal
burst gate width.
ADCLKS
Specifies the ADC clock
delay.
ADPDS
Specifies whether to use
ADC power-down.
NRDSW
Nonstandard detection
section test
NRZOFF
WCV-ID detection NRZ
section check
FSCOFF
WCV-ID detection FSC
section check
VTVH
Specifies WCV signal no-
image section processing
(only letter box signal is
valid).
Name and function
Table 15-2. Write Register Functions (13/14)
0000: H sync center + 2 s to
1111: H sync center + 5.75 s
Calculation of gate start position from the H sync center :
0000: 0.5 s to 1111: 4.25 s
Calculation of gate width : 0.25
00: 0 ns typically (setting prohibited)
01: 3 ns typically
10: 17.5 ns typically
11: 20.5 ns typically
0: Do not stop operation of ADC not in use.( High current drain)
1: Stop operation of ADC not in use. (Low current drain)
0: Normal mode
1: Test mode
0: NRZ section amplitude check on
1: NRZ section amplitude check off
0: FSC amplitude check on
1: FSC amplitude check off
00: Ordinary processing
01: Forced inter-frame Y/C separation
10: Forced inter-line Y/C separation
11: Forced through (composite signal is output.)
0.25
Data Sheet S16021EJ2V0DS
BGPS + 2.0 ( s)
Description
BGPW + 0.5 ( s)
Typical
value
0101
0011
PD64084
11
00
1
0
0
0
Initial
value
0101
0011
11
00
1
0
0
0
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