UPD64084 NEC, UPD64084 Datasheet - Page 43

• Manufacturer Part Number: UPD64084
• Description: THREE-DIMENSIONAL Y/C SEPARATION LSI WITH ON-CHIP MEMORY
• Manufacturer: NEC

02
03
SA
D7-D6
D5
D4
D3-D2
D1-D0
D7
D6
D5-D3
D2-D0
Bit
DYCOS
Specifies DYCO pin
input/output.
EXADINS
Specifies whether to
select external ADC.
MFREEZE
External memory test bit
PECS
Specifies a pedestal error
correction test bit.
EXCSS
Specifies whether to use
external C sync input.
CPP
Specifies the clamp pulse
width of internal ADC
HDP
Fine adjustment of
system horizontal phase
CDL
Fine adjustment of C
signal output delay
Name and function
-
Table 15-2. Write Register Functions (3/14)
In case of EXTDYCO = 0
In case of EXDYCO = 1
Note If HIZEN (SA16h, D4) = 1, then HI-Z.
0: Internal ADC
1: External ADC (digital video signal, converted from analog
0: Normal mode
1: Test mode (setting prohibited)
00: Normal setting
01: Test setting (setting prohibited)
10: Test setting (setting prohibited)
11: Test setting (setting prohibited)
00: Internally separated sync signal is always used (CSI input is
01: Sync signal input at the CSI pin is used during out-of-sync
1x: Sync signal input at the CSI pin is always used.
Undefined
0 : 2.2 s
1 : 1.1 s
000:
Fine-adjusts the horizontal-processing phase with respect to the
horizontal sync signal (0.28 s/step).
000:
Fine-adjusts the C signal phase with respect to the Y signal
(70 ns/step).
00: Y/C separation signal alternate output
01: Test mode (setting prohibited)
1x: Low* High impedance
00: DYCO9-0 : Output,
01: Test mode (setting prohibited)
1x: DYCO9-0 : Input (When EXADINS=0, Low
form, is input to the DYCO9 to DYCO0 pins)
not used).
state.
EXTDYCO9-0 : Input (When EXADINS=0, Low
EXTDYCO9-0 : Output
1.12 s to 100: ±0.00 s (Typ.) to 111: +0.84 s
280 ns to 100: ±0 ns (Typ.) to 111: +210 ns
Data Sheet S16021EJ2V0DS
Description
Note
),
Note
)
Typical
value
PD64084
100
100
10
00
01
0
0
0
0
Initial
value
100
100
10
00
01
0
0
0
0
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