UPD64084 NEC, UPD64084 Datasheet - Page 34

• Manufacturer Part Number: UPD64084
• Description: THREE-DIMENSIONAL Y/C SEPARATION LSI WITH ON-CHIP MEMORY
• Manufacturer: NEC

14.3 Setting of Digital Direct-Connected System
14.3.1
34
DO9 to DO0 (pins 6 to 15)
N3D (pin 3)
CSO (pin 4)
ALTF (pin 5)
OCP (pin 18)
CLK8 (pin 30)
FSCO (pin 47)
C20O (pin 54)
CKMD (pin 31)
WP1 (pin 35)
EXDAS (pin 58)
FSCI (pin 40)
See the pin connection and setting in the following table to digitally connect the PD64031A and PD64084 directly.
PD64031A Pin
Hardware setting
–
–
Direction
Signal
Table 14-1. Pin Setting for Digital Direct-Connection
–
–
–
–
–
–
DYCO0 to DYCO9 (pins 63 to 72)
LINE (pin 74)
CSI (pin 77)
ALTF (pin 73)
ST0 (pin 59)
CLK8 (pin 57)
FSCI (pin 54)
XI (pin 36)
FSCO (pin 51)
XO (pin 37)
Data Sheet S16021EJ2V0DS
PD64084 Pin
–
–
–
–
10-bit digital video signal interface
Three-dimension processing prohibiting flag
Register N3D1STEN of the PD64031A (SA01h:
D5) must be set.
Composite sync signal
The signal from the sync separation circuit
connected to the PD64031A is shared by the
Digital clamp clock (4f
Register ADCLKS of the PD64084 (SA15h: D7
and D6) must be set.
Clamp pulse for digital clamp circuit
Register ST0S of the PD64084 (SA07h: D1 and
D0) must be set.
System clock (8f
Register CLK8OFF of the PD64084 (SA07h: D4)
must be set.
Burst lock clock (connected via an analog switch)
20-MHz reference clock
Fixed to high level (external clock mode)
Connected to analog switch (control signal output)
This pin is controlled by register DIR3DYC of the
path.
Fixed to high level (digital output is valid)
Fixed to GND (f
Connected to analog switch
Open
PD64084.
PD64031A (SA08h: D7 and D6) to select a clock
SC
SC
generator is not used)
)
Function
SC
)
PD64084