K4T56163QI-ZCLCC SAMSUNG [Samsung semiconductor], K4T56163QI-ZCLCC Datasheet - Page 26

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K4T56163QI-ZCLCC

Manufacturer Part Number
K4T56163QI-ZCLCC
Description
256Mb I-die DDR2 SDRAM Specification
Manufacturer
SAMSUNG [Samsung semiconductor]
Datasheet
K4T56163QI
DQS
Note1
Note : DQS signal must be monotonic between Vil(dc)max and Vih(dc)min.
V
V
V
V
V
V
Setup Slew Rate
IL(dc)
IL(ac)
DDQ
REF(dc)
IH(ac)
IH(dc)
Falling Signal
Figure 8 - IIIustration of tangent line for tDS (single-ended DQS)
max
max
V
V
V
V
V
V
V
min
min
V
DDQ
IH(ac)
IH(dc)
IL(dc)
IL(ac)
SS
REF(dc)
nominal
SS
line
V
max
max
min
min
region
REF
=
tangent line[V
to ac
∆TF
∆TF
tDS
tangent
REF(dc)
line
26 of 42
Setup Slew Rate
Rising Signal
- Vil(ac)max]
tDH
nominal
line
=
∆TR
tangent line[Vih(ac)min - V
tDS
tangent
line
∆TR
tDH
V
REF
region
to ac
REF(dc)
Rev. 1.0 October 2007
]
DDR2 SDRAM

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