K4T56163QI-ZCLCC SAMSUNG [Samsung semiconductor], K4T56163QI-ZCLCC Datasheet - Page 38

• Manufacturer Part Number: K4T56163QI-ZCLCC
• Description: 256Mb I-die DDR2 SDRAM Specification
• Manufacturer: SAMSUNG [Samsung semiconductor]

20. Input waveform timing tDS with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the VIH(ac) level to the
21. Input waveform timing tDH with differential data strobe enabled MR[bit10]=0, is referenced from the differential data strobe crosspoint to the input sig-
22. Input waveform timing is referenced from the input signal crossing at the VIH(ac) level for a rising signal and VIL(ac) for a falling signal applied to the
23. Input waveform timing is referenced from the input signal crossing at the VIL(dc) level for a rising signal and VIH(dc) for a falling signal applied to the
K4T56163QI
device under test. See Figure 19.
device under test. See Figure 19.
differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL(ac) level to the differential data strobe crosspoint for
a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(dc)max and Vih(dc)min. See Figure 18.
nal crossing at the VIH(dc) level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the VIL(dc) level for
a rising signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(dc)max and Vih(dc)min. See Figure 18.
CK
CK
DQS
DQS
Figure 19 - Differential input waveform timing - tIS and tIH
Figure 18 - Differential input waveform timing - tDS and tDH
tIS
tDS
tIH
tDH
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tDS
tIS
tDH
tIH
V
V
V
V
V
V
V
DDQ
IH(ac)
IH(dc)
REF(dc)
IL(dc)
IL(ac)
SS
V
V
V
V
V
V
V
DDQ
IH(ac)
IH(dc)
REF(dc)
IL(dc)
IL(ac)
SS
max
max
min
min
Rev. 1.0 October 2007
max
max
min
min
DDR2 SDRAM