SSTUB32866BHLFT IDT, Integrated Device Technology Inc, SSTUB32866BHLFT Datasheet
SSTUB32866BHLFT
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Integrated Circuit Systems, Inc. 25-Bit Configurable Registered Buffer for DDR2 Recommended Application: • DDR2 Memory Modules • Provides complete DDR DIMM solution with ICS97ULP877, 98ULPA877A • Ideal for DDR2 400,533, and 667 Product Features: • 25-bit 1:1 or 14-bit 1:2 ...
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DCKE PPO REF D2 NC GND GND QERR D DODT GND GND GND GND RST G PAR_IN ...
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General Description This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are ...
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Ball Assignment ...
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Block Diagram for 1:1 mode (positive logic) RST REF DCKE DODT DCS CSR D1 NOTE: 1. Disabled in 1:1 configuration. 1165A—3/21/ OTHER CHANNELS 5 ICSSSTUB32866B Advance Information C1 QCKEA ...
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Block Diagram for 1:2 mode (positive logic) RST REF DCKE DODT DCS CSR D1 NOTE: 1. Disabled in 1:1 configuration. 1165A—3/21/ OTHER CHANNELS 6 ICSSSTUB32866B ...
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Device standard (cont'd) G2 RST D2•D3, 22 D5•D6, D8-D25 A3 REF PAR_IN G6 C0 Counter R Figure 6 Parity logic diagram for 1:1 register configuration (positive logic): C0=0, C1=0 1165A—3/21/07 ...
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Device standard (cont'd) G2 RST D2•D3, 11 D5•D6, D8-D14 A3 REF PAR_IN G6 C0 Counter R Figure 7 — Parity logic diagram for 1:2 register-A configuration (positive logic); C0=0, C1=1 ...
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Device standard (cont'd) G2 RST (internal node) D1•D6, 11 D8-D13 A3 REF PAR_IN 2•Bit Counter R Figure 8 Parity logic diagram for 1:2 register-B configuration (positive logic); ...
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Device standard (cont'd) RST DCS CSR act D1•D25 † Q1•Q25 PAR_IN † PPO QERR ‡ Figure 9 — Timing diagram for SSTU32866 used as a single device; C0=0, C1=0; After RST is switched from low to ...
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Device standard (cont'd) RST DCS CSR CK CK D1•D25 Q1•Q25 PAR_IN PPO QERR † Unknown input event Figure 10 Timing diagram for SSTU32866 used as a single device; C0=0, C1=0; † If the data is clocked in on the ...
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Device standard (cont'd) RST DCS † CSR † CK † CK † D1•D25 † Q1•Q25 PAR_IN † PPO QERR Figure 11 — Timing diagram for SSTU32866 used as a single device; C0=0, C1=0; † After RST is switched from ...
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Device standard (cont'd) RST DCS CSR CK CK D1•D14 † Q1•Q14 PAR_IN † PPO QERR# ‡ (not used) Figure 12 — Timing diagram for the first SSTU32866 (1:2 register-A configuration) device used in † After RST is switched from ...
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Device standard (cont'd) RST DCS CSR CK CK D1•D14 Q1•Q14 PAR_IN PPO QERR † (not used) Unknown input event Figure 13 — Timing diagram for the first SSTU32866 (1:2 register-A configuration) device used in † If the data is ...
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Device standard (cont'd) RST# DCS# † CSR# † † CK † CK# D1•D14 † Q1•Q14 PAR_IN † PPO QERR# (not used) Figure 14 — Timing diagram for the first SSTU32866 (1:2 register-A configuration) device used in pair; C0=0, C1=1; ...
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Device standard (cont'd) RST# DCS# CSR# CK CK# t act D1•D14 † Q1•Q14 PAR_IN †‡ PPO (not used) QERR# § Figure 15 — Timing diagram for the second SSTU32866 (1:2 register-B configuration) device used in † After RST# switched ...
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Device standard (cont'd) 1165A—3/21/07 ICSSSTUB32866B Advance Information 17 ...
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Device standard (cont'd) RST# DCS# † CSR# † CK † CK# † D1•D14 † Q1•Q14 PAR_IN † PPO (not used) QERR# Figure 17 — Timing diagram for the second SSTU32866 (1:2 register-B configuration) device used in † After RST# ...
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Register Configurations ...
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Absolute Maximum Ratings Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Supply Voltage . . . . . . . . . . ...
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Electrical Characteristics - 70° 1.8 +/-0.1V (unless otherwise stated SYMBOL PARAMETERS ( All Inputs I RESET = ...
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Timing Requirements (over recommended operating free-air temperature range, unless otherwise noted) SYMBOL PARAMETERS f Clock frequency clock Pulse duration, CK, CK HIGH or LOW Differential inputs active time (See Notes 1 and 2) ACT t Differential inputs ...
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CK Inputs Test Point Test Point LVCMOS RST Input t INACT ( 10% VOLTAGE AND CURRENT WAVEFORMS INPUTS ACTIVE AND INACTIVE TIMES t W Input V ICR VOLTAGE WAVEFORMS PULSE DURATION CK# ...
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LOAD CIRCUIT - HIGH-TO-LOW SLEW-RATE MEASUREMENT LOAD CIRCUIT - LOW-TO-HIGH SLEW-RATE MEASUREMENT Figure 7 ⎯ Output Slew-Rate Measurement Information (V Notes includes probe and jig capacitance All input pulses are supplied by generators having the following ...
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LVCMOS RESET# Waveform 2 Voltage Waveforms, open-drain output LOW-to-HIGH with respect to RESET# input Timing Inputs Output Waveform 1 Voltage Waveforms, open-drain output HIGH-to-LOW with respect to clock inputs Timing Inputs Waveform 2 Voltage Waveforms, open-drain output LOW-to-HIGH with respect ...
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CLK CLK Output 600mV I(P-P) t and t are the same as t PLH PHL Partial parity out voltage waveform, propagation Input Output and t ...
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SEATING PLANE A1 D TOP VIEW E ALL DIMENSIONS IN MILLIMETERS Min/Max 13.50 Bsc 5.50 Bsc 1.20/1.40 0.80 Bsc 11.50 Bsc 5.00 Bsc 1.00/1.20 0.65 Bsc Note: Ball grid total indicates maximum ball count for package. Lesser ...
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Revision History Rev. Issue Date Description 0.1 10/3/2005 Initial Release 0.2 1/13/2006 Updated Package Dimensions. 0.3 1/16/2006 Updated Package Dimensions. 0.4 10/25/2006 Added DC table notes 2 and 3 1165A—3/21/07 ICSSSTUB32866B Advance Information 28 Page # - ...